STA (Static Timing Analysis) Design Intern
Work with the Static Timing Analysis team to evaluate timing margins of ASIC/SoC digital designs and help ensure chips meet target performance with no timing errors. The role supports timing analysis runs, constraint management, timing fixes and automation to improve flow efficiency.
Entry-level internship for current undergraduate students (third-year or final-year). Requires commitment to an internship program and on-site attendance as noted below.
Perform STA tasks and assist engineers across the design flow.
Minimum required skills and commitments for the internship.
Third-year or final-year student currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, VLSI Systems, or a closely related field such as Physics or Mathematics. Student status and enrollment in a relevant undergraduate program are required.
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
