STA Silicon Design Engineer

Job Title

STA Silicon Design Engineer

Role Summary

Work on static timing analysis (STA) and timing signoff for IPs, subsystems, and full-chip flows. You will develop multi-mode/multi-corner timing constraints, drive pre-route timing checks and QoR cleanup, and support timing closure through ECO implementation.

This role sits within the silicon design/STA team and interfaces with RTL, physical design, and verification teams to ensure timing quality and handoff readiness for signoff.

Experience Level

Senior — typically 8+ years of relevant STA/timing, physical design, or EDA tool experience.

Responsibilities

Primary responsibilities include defining constraints, analyzing timing reports, and leading timing closure activities.

• Develop multi-mode, multi-corner SDC timing constraints compatible with RTL and signoff flows.
• Ensure SDC quality and run timing checks using industry tools (e.g., PrimeTime, Fishtail, GCA).
• Drive pre-route timing checks and QoR clean-up to eliminate SDC issues and ensure a clean handoff for STA.
• Lead timing closure for one or multiple subchip/subsystem or full-chip designs, including interface timing and DRV closure.
• Generate and apply timing ECOs using tools such as DMSA or Tweaker.
• Collaborate with physical design, RTL, and DFT teams to resolve timing and implementation issues.

Requirements

Must-have technical skills are listed first; followed by preferred or nice-to-have items.

• Must-have: Strong TCL/scripting skills for EDA tool automation and standalone Linux shell scripts.
• Must-have: Deep knowledge of SDC constraints and timing signoff methodology, including OCV/AOCV/POCV analysis.
• Must-have: Proven experience with timing analysis, interpreting timing reports, and resolving design- and constraints-related issues.
• Must-have: Familiarity with EDA timing tools such as Synopsys PrimeTime/Design Compiler; experience with Fishtail, Tweaker, Spyglass, or similar tools.
• Must-have: Practical understanding of physical design flow and ECO implementation for timing closure.
• Must-have: Understanding of DFT mode impacts on timing signoff.
• Nice-to-have: Experience with timing closure of high-frequency (>GHz) blocks and multimedia/video codec systems.
• Preferred: Prior experience building timing constraints in flat and hierarchical flows; leadership of subsystem/full-chip timing closure.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is specified.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.