STA Engineer (Top Level)

Job Title

STA Engineer (Top Level)

Role Summary

The STA Engineer will create and verify block- and top-level timing constraints, run static timing analysis (STA), drive timing closure, and generate timing ECOs for large hierarchical SoC/SiP designs. The role requires close collaboration with design teams, external IP providers, EDA vendors, and silicon/package teams.

Position is based in Barcelona and involves work on advanced technology nodes; visa sponsorship is available if required.

Experience Level

Senior-level — requires proven, hands-on experience with multiple tapeouts and complex top-level/block STA on large hierarchical designs. Specific years of experience are not listed.

Responsibilities

Primary responsibilities include:

• Developing and validating block-level and top-level timing constraints for multiple blocks and full-chip assemblies.
• Analyzing STA results, diagnosing timing issues, and driving timing closure across block and top-level partitions.
• Generating timing ECO scripts and coordinating fixes with block owners and physical design/CAD teams.
• Reviewing and improving constraint quality and coverage from internal and third-party IP providers.
• Setting up or tuning tool flows and distributed processing for large-scale timing runs when required.
• Providing STA expertise to design and implementation teams and mentoring junior engineers during block-level closure.
• Working with EDA vendors and external partners to validate flows and handle multi-scenario analyses.

Requirements

Must-have technical skills and experience:

• Proven experience on multiple tapeouts of high-performance SoCs or SiPs.
• Extensive experience with Synopsys PrimeTime, including DMSA for multi-scenario analysis.
• Strong TCL proficiency for timing analysis and automation.
• Experience using revision control systems, preferably Git.
• Hands-on experience managing very large hierarchical designs, including budgeting flows and context-aware block constraints.
• Knowledge of hyperscale or other techniques and distributed/threaded processing options for handling huge designs in PrimeTime.
• Ability to create and execute timing ECOs and push timing fixes into block-level physical design.
• Experience mentoring junior engineers and collaborating across cross-functional teams.
• Nice-to-have: experience with PrimeClosure.

Education Requirements

Master's or PhD in Computer Science, Microelectronics, or Physics.

About the Company

Company: Semidynamics

Headquarters: Barcelona, Spain

Semidynamics is a company specializing in infrastructure verification and automation solutions. They focus on optimizing resources and enhancing continuous integration processes in design verification. The team collaborates to maintain regression test infrastructure and develop efficient workflows.