STA Engineer

Job Title

STA Engineer

Role Summary

Member of the silicon design timing team responsible for Static Timing Analysis (STA) and timing constraint development for IP, subsystems and full-chip designs. Works with RTL, signoff flows and physical design teams to ensure timing closure and quality handoffs.

Role focuses on creating and validating multi-mode/multi-corner SDC constraints, driving pre-route timing checks and implementing timing ECOs to meet performance targets.

Experience Level

Senior — the role targets experienced engineers, typically 8+ years of relevant STA/timing experience.

Responsibilities

Primary responsibilities include development, validation and closure activities for timing constraints and signoff:

• Develop multi-mode / multi-corner timing constraints compatible with RTL and signoff flows.
• Ensure SDC quality and validate constraints using industry tools and checks.
• Drive pre-route timing checks and QoR cleanup to eliminate SDC issues before STA.
• Lead timing closure for one or multiple sub-chip/subsystem or full-chip designs, including interface timing and DRV closure.
• Generate timing ECOs and apply ECO implementations to achieve closure (using tools such as DMSA/Tweaker).
• Analyze timing reports to identify design and constraints-related issues and determine remediation paths.
• Collaborate with physical design and DFT teams to ensure signoff readiness across design corners.
• Automate and maintain scripts and flows used in timing analysis and ECO generation.

Requirements

Must-have technical skills and domain knowledge:

• Strong SDC constraints knowledge and timing signoff methodology (multi-mode / multi-corner).
• Proven experience with STA and timing closure for high-frequency blocks and subsystems.
• Mandatory strong TCL/scripting skills for EDA flows and standalone Linux scripting.
• Practical experience with EDA timing tools (e.g., Synopsys PrimeTime, Spyglass, Fishtail, Tweaker).
• Understanding of OCV/AOCV/POCV analyses and their impact on signoff.
• Good knowledge of physical design flow and implementing ECOs.
• Familiarity with DFT mode requirements for timing signoff.

Nice-to-have:

• Experience building timing constraints in both flat and hierarchical flows.
• Experience driving full-chip timing closure and coordinating across subsystems.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering as stated by the employer.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.