STA/Constraints Engineer

Job Title

STA/Constraints Engineer

Role Summary

Responsible for developing full-chip constraints and driving timing closure for SOC and subsystem integration. Works with SOC architects, physical design, synthesis, verification, power signoff and EDA vendors to deliver timing signoff and improve constraints methodology.

Acts as a technical mentor to design engineers and coordinates cross-functional teams on timing-related milestones.

Experience Level

Mid-level — typical candidates have several years of industry experience (approximately 3–7 years) in STA, constraints, or physical design-related roles.

Responsibilities

Primary duties include timing constraints development, analysis, and signoff across SOC projects.

• Own end-to-end timing constraints and timing signoff for SOC and subsystem integration.
• Collaborate with SOC Architecture to define clocks and statistical timing targets.
• Create and verify SDC files; ensure correct clock setup and constraints implementation.
• Perform static timing analysis (STA) and drive timing closure, including shift-left activities.
• Analyze timing margins (LVF/SSTA/variation) and work with timing methodology teams on node-specific issues.
• Coordinate with CAD and EDA vendors to enhance timing-closure and constraints methodologies.
• Support CDC/lint checks, netlist quality reviews, lower-power implementation, and RTL/netlist interactions with PD teams.
• Provide guidance and mentorship to design engineers on timing-related tasks and schedules.

Requirements

Key must-have skills and constraints for the role; preferred items are listed separately.

• Must-have: Industry experience in STA, constraints, and timing signoff.
• Must-have: Expert user of Synopsys PrimeTime/GCA (PT/GCA).
• Must-have: Proficiency in scripting (Perl, TCL, Shell, Python) and familiarity with Verilog RTL.
• Must-have: Experience on large digital ASIC projects and strong communication/presentation skills.
• Must-have: Authorization to work in the United States; this role is not eligible for visa sponsorship.
• Nice-to-have: Experience with ICC2/FT for physical implementation.
• Nice-to-have: Knowledge of DFT timing concepts, MBIST, floorplanning, placement, CTS and routing flows.
• Nice-to-have: Background in physical design, synthesis/implementation, and low-power design methodology.

Education Requirements

Bachelor's or Master’s degree in Microelectronics, Integrated Circuit Science, or a related field preferred.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.