SSP - CIC Analog Circuit Simulation Internship (QA Engineer Intern)

Job Title

SSP - CIC Analog Circuit Simulation Internship (QA Engineer Intern)

Role Summary

Two-month summer internship (July–August 2026) on the CIC Analog Circuit Simulation team developing and validating Siemens EDA analog circuit simulators (Solido Simulation Suite). Hybrid position based in Cairo, focused on quality assurance, test automation, performance analysis, and usability feedback.

Interns will work with development and marketing teams to design and execute tests, analyze results, diagnose issues, and contribute automated checks and test coverage improvements.

Experience Level

Entry-level / Internship. Intended for 3rd- or 4th-year undergraduate students; minimal professional experience required.

Responsibilities

Primary responsibilities focus on validating simulator accuracy, performance, and usability and on building automated tests and coverage metrics.

• Design and execute test plans and innovative test scenarios reflecting real customer models and use cases.
• Validate simulator accuracy and assess performance vs. accuracy trade-offs.
• Analyze test results, diagnose problems, document defects, and propose potential fixes.
• Create automated accuracy checks and regression tests for real-world analog designs.
• Develop test cases using analog design languages (SPICE, Verilog‑A) to evaluate new features.
• Measure and report test coverage; recommend and implement coverage improvements.
• Evaluate usability (GUI) attributes and provide feedback to improve user experience.
• Analyze large-scale performance data using modern analysis methods and apply AI/ML concepts where appropriate.
• Collaborate with cross-functional teams and document test plans, results, and bug reports.

Requirements

Concise list of must-have and nice-to-have skills for the internship.

• Must-have: Experience with analog circuit design and use of commercial analog simulators; familiarity with software QA methodology including regression testing and test coverage analysis.
• Must-have: Strong written and verbal communication skills and ability to document test plans and defects clearly.
• Must-have: Self-motivated, detail-oriented team player able to work independently and in a team environment.
• Nice-to-have: Familiarity with EDA analog design environments (e.g., Cadence Virtuoso, Synopsys Custom Designer, Tanner S-Edit).
• Nice-to-have: Knowledge of AI/ML and Large Language Model (LLM) concepts and experience with API testing.
• Nice-to-have: Experience with shell scripting, UNIX, and general programming or development experience.
• Nice-to-have: Experience writing Verilog‑A descriptions.

Education Requirements

3rd- or 4th-year undergraduate student in Computer Science, Computer Engineering, or Electrical Engineering. (Undergraduate enrollment in a related technical field is required; no alternative degree or explicit equivalent-experience language provided.)

About the Company

Company: Siemens

Headquarters: Munich, Germany

Siemens EDA is a leading global provider of Electronic Design Automation (EDA) products and systems. Their innovative solutions enable companies to enhance the development of electronic products efficiently and effectively, keeping pace with the complex demands of technology and physics. Siemens is committed to delivering advanced workflow solutions that integrate both EDA and MCAD tools for multi-domain design and manufacturing in the semiconductor industry.