SSG Design Engineering Intern (Fall 2026)
Internship within Cadence's Silicon Solutions Group (SSG) R&D team in San Jose working on the Janus Network-on-Chip (NoC) IP product. Projects focus on digital RTL design or design verification and require collaboration with Design, Verification, and Physical Design teams.
Entry-level internship.
Intern will be assigned one of two primary streams and will work under mentor supervision.
Must-have technical skills and working habits for success in the internship.
Currently enrolled in a BS or MS program in Electrical Engineering, Computer Engineering, or a closely related major.
California hourly range provided in the posting: $35/hr to $62/hr. Candidates may also be eligible for incentive compensation and benefits; exact compensation will vary by qualifications and location.
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
