Sr Test Engineer

Job Title

Sr Test Engineer

Role Summary

Lead test engineering for Gate drivers, Power Stages and Isolators at the Hukou site. Own ATE test program development, test architecture, NPI test builds, DfT coordination with design teams, yield optimization and technical mentoring.

The role requires hands-on test platform expertise, hardware design review capability for high-voltage/high-power applications, and cross-functional leadership to deliver production-ready test solutions.

Experience Level

Senior — 8–10+ years in semiconductor test development with delivered mixed-signal or power-management products to mass production.

Responsibilities

Primary responsibilities include defining test strategy, driving NPI to release, and improving yield and cost of test.

• Define and architect cost-effective ATE test solutions for Gate drivers, Power Stages and Isolators on Cohu DMDx, DMDx DxV and Acco STS8300 platforms.
• Lead design reviews and development of complex test interface hardware (load boards, probe cards); resolve signal integrity and thermal issues for high-voltage/high-power and GaN devices.
• Drive NPI test builds from concept through release; coordinate DfT discussions with IC design and validation teams to ensure coverage and characterization completion.
• Implement statistical analysis and test data strategies to improve yield and reduce Cost of Test (CoT), including aggressive Test Time Reduction (TTR) tactics.
• Act as technical focal point for cross-functional collaboration with design, product engineering, and OSAT partners; provide mentorship and technical leadership to test engineers.

Requirements

Must-have technical skills and experience required to perform the role.

Must-have:

• Deep hands-on experience with ATE test program development and scalable test libraries/drivers.
• Proven experience with C/C++ and VB for test development and automation frameworks.
• Practical knowledge of Cohu DMDx, DMDx DxV and Acco STS8300 tester architectures and resource constraints.
• Experience with statistical data-analysis tools and techniques (examples: JMP, Datapower, Galaxy, Dana) for yield improvement.
• Experience testing GaN or other high-voltage/high-power devices and addressing SI/thermal challenges.
• Experience in reviewing and specifying test interface hardware (load boards, probe cards) for high-performance tests.
• Demonstrated ability to lead NPI test builds and collaborate across international teams and OSATs.

Nice-to-have:

• Experience with Teradyne ETS-800 tester platform.
• Deep knowledge of DfT techniques (scan, MBIST, analog DfT).
• Scripting for automation and data workflows (Python, Perl).
• Advanced PCB review skills for complex multi-layer high-speed/high-power designs (Altium/Cadence).

Education Requirements

Bachelor's degree in Electrical Engineering, Electronics or a related field is required; Master's degree strongly preferred.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.