Sr Staff Timing Design Engineer (2)

Job Title

Sr Staff Timing Design Engineer (2)

Role Summary

Lead timing (STA) or test (DFT) design activities for MCU/MPU products in the consumer, industrial and IoT markets. Work in a global backend team to improve product quality, performance and cost competitiveness using modern EDA flows and AI-assisted techniques.

Experience Level

Senior. The posting indicates a senior/staff-level role; specific years of experience are not stated.

Responsibilities

Primary technical and cross-team responsibilities:

• Perform static timing analysis (STA) using tools such as Synopsys Tempus or PrimeTime.
• Perform test/DFT implementation using tools such as Mentor/Siemens Tessent or Infineon Modus.
• Lead backend timing and test design tasks, driving quality, performance and cost improvements for silicon designs.
• Collaborate with cross-functional and cross‑country teams (Japan, China, Germany, Vietnam, India) on implementation and signoff.
• Integrate modern EDA flows and AI-assisted techniques into the timing/test design process.
• Generate design deliverables and documentation required for tapeout and verification.

Requirements

Minimum and preferred qualifications:

• Must-have: Practical knowledge or experience in either timing design (STA) or test design (DFT).
• Nice-to-have: Experience using commercial EDA tools for timing or test (examples: Cadence, Synopsys, Siemens/Mentor).
• Nice-to-have: Prior LSI/backend experience for MCU/MPU designs and familiarity with signoff flows.

Education Requirements

Not specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.