Sr. Staff RTL Design Engineer - PCIe

Job Title

Sr. Staff RTL Design Engineer - PCIe

Role Summary

Senior RTL design engineer responsible for micro‑architecture, RTL implementation, and integration of PCIe/CXL subsystems within Marvell's Data Centre Engineering (Compute & Storage) organization. The role leads design execution through verification, physical design handoff, and silicon bring‑up, and provides technical leadership and mentoring within the PCIe/CXL domain.

Experience Level

Senior-level — typically requires 8+ years of relevant RTL design experience.

Responsibilities

Primary responsibilities include subsystem architecture-to-silicon delivery and cross-functional collaboration.

• Define and drive PCIe/CXL subsystem micro-architecture and RTL implementation.
• Translate architecture requirements into robust RTL and ensure integration across IP and subsystems.
• Collaborate with verification teams on test plans, debug, and coverage closure.
• Work with Physical Design and DFT teams to ensure PD-ready and DFT-ready RTL.
• Support silicon bring-up and post-silicon debug with firmware and validation teams.
• Improve design quality, enforce coding best practices, and promote reuse across projects.
• Participate in design and milestone reviews and lead cross-functional technical discussions.
• Mentor junior designers and provide technical leadership within the PCIe/CXL design domain.

Requirements

Must-have technical skills and hands-on experience.

• 8+ years of RTL design experience focused on high-performance subsystems.
• Proven track record delivering complex PCIe/CXL IP or subsystems from architecture to RTL closure.
• Hands-on SystemVerilog / Verilog RTL development experience.
• Deep understanding of PCIe protocol layers (link, transaction, PHY) and CXL (CXL.io, CXL.cache, CXL.mem).
• Experience with ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE).
• Design experience for high-performance, low-latency datapaths, including ordering, coherency, and error handling.
• Strong knowledge of clocking, resets, CDC/RDC, low-power techniques, and performance optimization.
• Experience supporting lint, CDC/RDC analysis, synthesis, and design sign-off flows.
• Proficient debugging of functional and performance issues at subsystem and SoC levels.
• Familiarity with industry EDA tools (Synopsys, Cadence, Mentor/Siemens) and version control systems (Git, SVN).
• Proficient scripting skills (Tcl, Perl, Python).
• May require eligibility for access to export-controlled technology; candidates may undergo export license review.
• Interview integrity: use of AI tools during interviews is not permitted.

Education Requirements

Master's or Bachelor's degree in Electronics / Electrical Engineering (Master’s preferred). The posting specifies a Master’s/Bachelor’s degree in Electronics/electrical Engineering.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.