Sr. Staff / Principal PCIe Subsystem Architect

Job Title

Sr. Staff / Principal PCIe Subsystem Architect

Role Summary

Define and deliver high-performance I/O subsystem architecture for next-generation datacenter AI accelerator products. Work within the ASIC Engineering team to drive requirements from accelerator card and server level through rack-scale deployments.

Experience Level

Senior-level. Posting provides degree-plus-experience guidance: Bachelor's +10+ years, Master's +8+ years, PhD +6+ years; the posting also references ASIC-design minimums of Bachelor's +6+ years, Master's +5+ years, PhD +4+ years for relevant ASIC experience.

Responsibilities

Primary responsibilities include architecture definition, system-level requirements, and cross-team coordination for datacenter I/O subsystems.

• Define PCIe, CXL, UCIe, NVMe, and Ethernet subsystem architecture for accelerator and server platforms.
• Drive system-level requirements and trade-offs across accelerator cards, hosts, and rack deployments.
• Specify and validate PCIe Gen6/Gen7 features (FLIT mode, PAM4 signaling, link training, latency, error handling).
• Design for error containment and recovery (AER, DPC, CRS, FLR, reset separation).
• Specify I/O virtualization and isolation requirements (SR-IOV, SIOV, PF/VF isolation).
• Address RAS, telemetry, reliability, and security requirements for server-class SoCs and accelerator subsystems.
• Consider signal-integrity, retimers, PHY/SerDes, and system-level validation constraints.
• Collaborate with customers, product management, systems teams, and cross-functional stakeholders to gather requirements and drive alignment.
• Work effectively in international, multi-site engineering teams.

Requirements

Must-have skills and experience required for the role.

• Deep expertise in PCIe and other high-speed interfaces used in datacenter products.
• Experience architecting I/O subsystems for datacenter accelerator or server products at card and system scale.
• Knowledge of PCIe ordering models, DMA flows, and high-speed serial interface behavior.
• Experience with PCIe error containment, recovery mechanisms, and system-level error handling.
• Experience with I/O virtualization/isolation technologies and related software-visible requirements.
• Understanding of RAS, telemetry, reliability, and security requirements for server SoCs.
• Ability to create architecture specifications, requirement documents, and clear technical summaries.
• Ability to engage with customers and cross-functional teams to gather requirements and drive alignment.

Nice-to-have:

• Familiarity with UCIe, UALink/UAL, UEC, and other emerging AI interconnects.
• Experience with PCIe firmware/BIOS/driver/system-software interactions.
• Knowledge of PCIe CEM standards, add-in card constraints, retimers, and signal-integrity considerations.
• Experience with high-speed SerDes, PHY technologies, PAM4 signaling, and power/performance tradeoffs.

Education Requirements

Posting specifies Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, Science, or a related technical field. Degree-plus-experience combinations are provided (e.g. Bachelor's with 10+ years, Master's with 8+ years, PhD with 6+ years) and alternate ASIC-design minimums (Bachelor's with 6+ years, Master's with 5+ years, PhD with 4+ years).

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.