Sr Staff Package Design Engineer

Job Title

Sr Staff Package Design Engineer

Role Summary

Lead design and development of semiconductor package and interconnect solutions focused on power SiP/modules, wafer-level chip-scale packages (WLCSP), multi-chip modules, embedded-die/capacitor assemblies and power device packaging. Work within Manufacturing in Tempe to qualify technologies, enable production ramp, and coordinate with OSATs/CMs, Product, Reliability and Quality teams for consumer, industrial and automotive power applications.

Experience Level

Senior — 10–15 years of relevant package development experience preferred.

Responsibilities

Accountable for technical development, qualification, and production readiness of package solutions.

• Design and develop package and interconnect methods for power SiP/modules, WLCSP, multi-chip modules and power device packaging.
• Develop Cu RDL with seed layer on IC wafers and backside metal deposition following grinding.
• Develop wafer-thinning processes including Taiko BG and glass carrier bonding.
• Define substrate architecture, via/die interconnection, materials choices and PCB interface requirements.
• Qualify package technologies for consumer, industrial and automotive power applications.
• Benchmark, select and qualify materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).
• Plan and run DOE with OSAT/CM to optimize processes and establish production specifications and controls.
• Work with Product and Reliability teams to complete qualifications within required timelines and resolve process-integration issues.
• Ensure smooth transition to production, implement ramp monitoring and maintain production quality controls.
• Participate in packaging roadmap development and maintain package design rules.

Requirements

Core technical skills and interpersonal capabilities required for the role.

• Extensive experience in package development emphasizing power SiP/modules, wafer-level packaging and flip-chip LGA.
• Strong understanding of substrate-based or embedded-die/capacitor SiP architectures and assembly processes.
• Experience with qualification methods, SPC and statistical analysis tools for process control.
• Experience working with OSATs and CMs on process development and optimization.
• Strong interpersonal, verbal and written communication skills; ability to present technical results clearly.
• Strong analytical and presentation skills.
• Nice-to-have: familiarity with Cu FSM/BGBM technologies.

Education Requirements

Doctorate, Master’s or Bachelor’s degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.