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Sr Staff Mixed Signal Verification Engineer

Synopsys
September 06, 2026
Full-time
On-site
Hyderabad, Telangana, India
Verification Jobs, Level - Senior

Job Title

Senior Staff Mixed-Signal Verification Engineer

Role Summary

Lead mixed-signal (AMS) verification for complex IP projects, owning verification strategy, sign-off, and infrastructure. Work closely with analog designers, digital verification teams, modeling groups, and architects to ensure robust verification across block and subsystem integration.

Experience Level

Senior β€” typically 8+ years of hands-on AMS verification experience, with prior ownership of verification sign-off for mixed-signal designs.

Responsibilities

Primary responsibilities include defining methodology, building environments, and driving sign-off for mixed-signal verification.

  • Own end-to-end AMS verification strategy, test plans, coverage models, and sign-off for mixed-signal blocks and subsystems.
  • Design and maintain UVM/SystemVerilog verification environments that integrate Verilog-A/Verilog-AMS behavioral models and mixed-signal simulators.
  • Debug analog-digital interface issues, simulation convergence problems, and cross-domain failures using waveform analysis and AMS debug tools.
  • Develop assertions, monitors, scoreboards, and automated verification infrastructure focused on catching real silicon bugs.
  • Improve AMS simulation efficiency, optimize regression flows, and reduce debug turnaround time.
  • Collaborate with analog designers, digital verification engineers, modeling teams, and architects to align verification with design intent.
  • Mentor verification engineers, review test plans/environments, and drive AMS best practices across the team.

Requirements

Must-have technical skills and relevant experience; a short list of preferred additions.

  • Must-have: 8+ years of hands-on AMS verification with proven ownership of verification sign-off for mixed-signal designs.
  • Expert-level proficiency in SystemVerilog and UVM, including coverage-driven verification and constrained-random methodologies.
  • Experience with Verilog-A and Verilog-AMS for behavioral modeling and mixed-signal simulation.
  • Solid understanding of analog circuit behavior (bias circuits, regulators, PLLs, ADCs, DACs, or similar mixed-signal blocks).
  • Experience with AMS simulators (Spectre AMS, Xcelium AMS, or similar) and waveform debug tools.
  • Strong scripting skills (Python, Perl, or Tcl) for automation and regression management.
  • Nice-to-have: Experience with AI/ML-based verification techniques or automation frameworks.

Education Requirements

Not specified.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-09-03