Sr. Staff Hardware Design Engineer

Job Title

Sr. Staff Hardware Design Engineer

Role Summary

Lead the architecture and implementation of a Message Signaled Interrupt (MSI) Translation Engine (MTE) to enable secure, low-latency interrupt translation for RISC-V virtualization across embedded to server-class SoCs. Work with core MMU, architecture, verification, and physical design teams to deliver scalable Chisel-based RTL IP.

This role targets memory isolation, interrupt translation, and system-level integration for data center, automotive, and HPC applications.

Experience Level

Senior — 7+ years of industry experience in RTL design and memory systems.

Responsibilities

Primary responsibilities for the MTE lead role.

• Own the microarchitecture of the MSI Translation Engine to meet latency and throughput targets.
• Develop modular, highly configurable RTL generators using Chisel (Scala).
• Design and optimize the MTE memory hierarchy, including TLBs, MSHRs, and local metadata caches.
• Align MTE behavior with RISC-V Advanced Interrupt Architecture (AIA) and H-extension specifications.
• Define verification plans and collaborate with DV teams to cover complex corner cases (e.g., page faults during interrupt translation).
• Work with Physical Design to attain timing closure on advanced process nodes.
• Collaborate cross-functionally with Core MMU, architecture, and system teams to integrate the MTE into SoC interconnects and device flows.

Requirements

Key must-have skills and notable nice-to-have items.

• Must-have: 7+ years industry experience in RTL design for memory management, interrupt controllers, or complex SoC IP.
• Must-have: Proven knowledge of TLB design, MSHRs, and cache controller behavior.
• Must-have: Expertise with IOMMU mechanisms, two-stage address translation, and virtualization concepts.
• Must-have: Advanced proficiency in SystemVerilog or Verilog and strong engineering practices for maintainable RTL.
• Must-have: Protocol mastery of AMBA interfaces, specifically AXI4.
• Must-have: Strong written and verbal communication skills in English; ability to document microarchitectural specifications.
• Preferred / Nice-to-have: Experience with Chisel/Scala and object-oriented or functional languages (Scala, C++, Java).
• Preferred / Nice-to-have: Familiarity with PCIe stack (ATS, PRI) and RISC-V LTI for offloaded translation.
• Ability to pass background and reference checks; right to work in France and export-control authorization may be required.

Education Requirements

MS or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.