Sr. Staff Engineer, Timing Methodology & Signoff

Job Title

Sr. Staff Engineer, Timing Methodology & Signoff

Role Summary

Lead timing methodology, analysis, and signoff across block and SoC designs to achieve predictable timing convergence from architecture to silicon. Collaborate with RTL, DFT, physical design, IP, bring-up, and validation teams to define signoff strategy and ensure strong pre-silicon to post-silicon correlation.

This role focuses on timing convergence for advanced FinFET nodes and ultra-low-power designs; ownership includes methodology, constraints, signoff, and automation.

Experience Level

Senior — typically requires 8+ years of relevant experience in static timing analysis and timing signoff.

Responsibilities

Primary responsibilities include defining methodology and driving timing to closure across IP, blocks, and SoC.

• Own end-to-end timing convergence and signoff strategy (block → SoC → post-silicon).
• Develop and maintain timing flows, constraints, and analysis methodologies.
• Lead signoff activities: corner definition, timing margining, ECO strategy, extraction and analysis.
• Perform glitch/noise analysis and evaluate power/timing trade-offs for ultra-low-power designs.
• Drive block-level closure and SoC-level timing correlation and verification.
• Coordinate with RTL, DFT, physical design, IP, bring-up, and validation teams to ensure correlation and closure.
• Automate scripts and flows (TCL, Python) to improve scalability and team efficiency.
• Monitor STA advancements and adapt methodologies for new process technologies and multi-patterning nodes.

Requirements

Must-have technical skills and constraints for the role.

• 8+ years of experience in timing analysis, convergence, and signoff.
• Deep expertise in static timing analysis (STA) with Synopsys PrimeTime or Cadence Tempus.
• Proven experience with block-level and SoC-level timing closure in advanced process nodes (FinFET and multi-patterning).
• Solid understanding of digital design and timing fundamentals.
• Hands-on experience with industry EDA tools from Synopsys and Cadence.
• Proficiency in scripting (TCL, Python, or equivalent) to build automation and flows.
• Strong problem-solving skills and ability to drive cross-functional engineering issues to closure.
• Excellent communication and collaboration skills across engineering teams.
• Work authorization: Must be currently authorized to work in the United States and have an approved immigrant petition that supports H-1B extensions beyond six years or allows priority date retention.

Nice to have:

• Experience with placement-and-route tools (Fusion Compiler, Innovus).

Education Requirements

Not specified.

About the Company

Company: Ambiq

Headquarters: Austin, TX, United States

Semiconductor company developing ultra-low-power microcontroller units (MCUs) and system-on-chip (SoC) platforms for battery-powered and edge devices, focusing on low-power IP, RTL, and production silicon solutions.