Sr. Staff Engineer - Timing Methodology

Job Title

Sr. Staff Engineer - Timing Methodology

Role Summary

Lead timing methodology and static timing analysis (STA) activities to drive timing closure from block level through SOC signoff. Work with RTL designers, DFT, IP vendors, and post-silicon teams to define methodology, develop flows, and resolve timing convergence and correlation issues.

Collaborate across physical design and verification teams to balance timing, power, and performance for advanced FinFET processes and modern multi-patterning technologies.

Experience Level

Senior — minimum 8 years of professional experience in timing analysis, STA, and timing convergence.

Responsibilities

Primary technical and coordination responsibilities:

• Define and implement timing methodology and flows for block and SOC-level timing closure using Tempus or PrimeTime.
• Own timing convergence and signoff processes: corner/condition definition, extraction, margining, and correlation with silicon.
• Perform signoff timing analysis, glitch/noise analysis, and implement timing ECOs to meet PPA targets.
• Drive timing constraints definition and verification in collaboration with RTL teams and IP vendors; manage timing collateral for hard IP, standard cells, and memories.
• Coordinate interplay and trade-offs between timing and power, and define PVTRc or equivalent corners.
• Partner with post-silicon bring-up and test teams to validate pre-silicon timing assumptions and improve correlation.
• Continuously improve STA methodologies and automation scripts to increase efficiency and repeatability.

Requirements

Key qualifications and skills.

• Must-have: Minimum 8 years of experience in static timing analysis and timing convergence for digital SOCs.
• Must-have: Proven expertise with industry STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Must-have: Solid understanding of digital circuit design principles and timing closure strategies.
• Must-have: Proficiency with industry EDA toolsets (Synopsys, Cadence) and timing/extraction flows.
• Must-have: Experience scripting for automation (TCL, Python).
• Must-have: Strong analytical, problem-solving, and communication skills; able to work cross-functionally.
• Must-have: Must be currently authorized to work in the United States; the company will not sponsor visas for this role.
• Nice-to-have: Experience with place-and-route tools (Synopsys Fusion Compiler, Cadence Innovus) and advanced process nodes (FinFET, multi-patterning).

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, or a related technical field is required.

About the Company

Company: Ambiq

Headquarters: Austin, TX, United States

Semiconductor company developing ultra-low-power microcontroller units (MCUs) and system-on-chip (SoC) platforms for battery-powered and edge devices, focusing on low-power IP, RTL, and production silicon solutions.