Sr Staff Engineer, Synthesis and STA

Job Title

Sr Staff Engineer, Synthesis and STA

Role Summary

Senior backend design engineer responsible for RTL-to-gate conversion, constraint development, and timing closure for complex SOC blocks and full-chip designs. The role focuses on synthesis, physical-aware optimizations, static timing analysis (STA), and cross-functional collaboration with place-and-route and verification teams to meet PPA targets.

Experience Level

Senior — approximately 10–13 years of experience in synthesis and STA closure as specified in the posting.

Responsibilities

Deliver synthesis and STA solutions from block to full-chip level, maintain constraints, and drive timing closure.

• Plan and execute hierarchical and flat physical-aware synthesis flows to generate optimized gate-level netlists and meet PPA targets.
• Perform block-level and full-chip STA across multi-mode, multi-corner scenarios and drive timing signoff to closure.
• Develop and manage SDC constraints and UPF files for functional and DFT modes; coordinate top-level constraint integration.
• Collaborate with PNR/clock-tree teams to identify clock- and timing-related optimizations and reduce congestion.
• Implement and verify UPF-based low-power architectures and multi-voltage domain strategies.
• Use formal equivalence checking (LEC) to ensure RTL-to-netlist equivalence and resolve mismatches.
• Automate flows and create utilities using Tcl, Python, or Perl to improve turnaround time and reproducibility.
• Mentor junior engineers and provide technical leadership on closure strategies.

Requirements

Key technical and professional requirements. Items marked "Must-have" are essential; "Nice-to-have" are beneficial.

• 10–13 years of relevant experience in synthesis and STA closure on complex designs.
• Proven ability to achieve timing closure on high-frequency designs and propose PPA-driven optimizations.
• Experience with industry EDA tools such as Fusion Compiler, Innovus, PrimeTime, Tempus, VCLP, and LEC.
• Strong knowledge of static timing analysis, power analysis, and signal integrity concepts.
• Advanced scripting skills (Tcl, Python, or Perl) for flow automation and tool integration.
• Effective communication and teamwork skills for cross-functional collaboration.

• Experience mentoring or formally coaching junior engineers.
• Prior work on multi-domain UPF management and large full-chip closure projects.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.