Sr. Staff Engineer, Static Timing Analysis (STA)

Job Title

Sr. Staff Engineer, Static Timing Analysis (STA)

Role Summary

Lead block-level STA signoff and contribute to full-chip timing and power closure for advanced-node silicon. Work closely with physical design, synthesis, and verification teams to drive timing and power closure to meet PPA targets.

Join a backend/STA team focused on delivering repeatable signoff flows, automation, and high-quality closure for complex designs.

Experience Level

Senior — typically requires 8+ years of hands-on experience in STA and timing/power closure for advanced process nodes.

Responsibilities

Execute STA and closure activities, own deliverables, and improve team flows and automation.

• Own and execute block-level STA signoff and contribute to full-chip timing closure for advanced process nodes.
• Perform STA debugging and closure (setup/hold, recovery/removal, clock gating, CDC-related timing assumptions) and drive fixes with design/PD teams.
• Develop, validate, and maintain timing constraints (SDC) including clocks, generated clocks, exceptions, IO constraints, and mode/corner coverage.
• Run and analyze power signoff/support flows and correlate timing/power impacts of ECOs.
• Support timing and power ECO generation; validate fixes through signoff checks and regression testing.
• Collaborate with synthesis/implementation teams to ensure tool correlation and correct interpretation of constraints and physical effects (parasitics, AOCV/POCV, derates).
• Build and maintain automation to improve STA productivity, reporting, and regression quality (TCL/Python/Perl).
• Contribute to STA methodologies, checklists, and best practices; mentor junior engineers as needed.

Requirements

Key technical skills and experience required or strongly preferred.

• 8+ years of relevant STA / timing closure experience (block ownership expected; full-chip exposure preferred).
• Proven hands-on STA signoff experience across modes and corners, including MMMC concepts.
• Constraints development and validation (SDC) experience.
• Strong timing-closure debugging and ECO validation skills.
• Proficiency with PrimeTime (required); PrimePower/PT-PX and PrimeClosure/Tweaker preferred.
• Experience with power analysis/support flows and correlating timing and power impacts of ECOs.
• Strong scripting skills in TCL (required); Python and/or Perl preferred for automation.
• Working knowledge or exposure to Fusion Compiler/ICC2 or Design Compiler and parasitic extraction concepts (e.g., StarRC) is preferred.
• Understanding of low-power and high-frequency design considerations; UPF awareness is a plus.
• Clear communicator, strong analytical and debugging skills, and ability to work with minimal supervision across global teams.

Education Requirements

Requires a Bachelor's or Master’s degree (BE/BTech/MTech or equivalent) in Electronics/Electrical Engineering or a related technical field, or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.