Sr Staff Engineer, Power Integrity (PI), Signoff Lead

Job Title

Sr Staff Engineer, Power Integrity (PI), Signoff Lead

Role Summary

Primary technical owner for IR drop and power delivery signoff of high-speed CPU designs. Lead development of sign-off criteria, advanced power analysis methodologies, and automation of static and dynamic power/IR flows.

Work closely with Physical Design, Power, and packaging teams to ensure robust, power-density-aware power grids and accurate power readouts for signoff.

Experience Level

Senior-level. Requires 10+ years of experience in Physical Design.

Responsibilities

Core responsibilities include driving power integrity signoff and developing automated analysis flows:

• Serve as the subject-matter expert for dynamic and static IR signoff; define pass/fail criteria and margins.
• Architect power grid (PG) designs and optimize bump maps to meet power-density requirements.
• Lead automation and scaling of IR drop analysis flows, collaborating with PD and Power teams.
• Develop and integrate PrimeTime-PX (PTPX) flows for accurate vector-driven and vectorless power readouts.
• Drive PI closure for high-speed CPU implementations and coordinate cross-functional signoff activities.

Requirements

Must-have technical skills and conditions:

• Authoritative experience with dynamic and static IR signoff processes and criteria.
• Expertise with Ansys RedHawk or equivalent IR analysis tools.
• Hands-on experience in PG grid design and bump placement guided by complex power-density constraints.
• Practical experience with PrimeTime-PX (PTPX) for vector-driven and vectorless power readouts.
• Proven record delivering power-integrity closure for high-speed CPU architectures.
• Solid understanding of Physical Design flow and low-power implementation techniques.
• 10+ years of experience in Physical Design.
• Must be able to work in India and pass background/reference checks; position may require export-control authorization or successful licensing.

Nice-to-have:

• Hands-on experience with 3D IC design and package-silicon co-design.

Education Requirements

Minimum qualification: Bachelor's or Master's degree (degree field not specified). The posting also requires 10+ years of Physical Design experience. No explicit statement that equivalent practical experience substitutes for the degree.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.