Sr. Staff Engineer, IP Design (ASIC)
SK hynix AmericaJob Title
Sr. Staff Engineer, IP Design (ASIC)
Role Summary
Join the SoC Design team responsible for controller and high-speed interface IP for high-performance SSDs. The role owns design and verification of interface IP from micro-architecture and RTL through timing closure and silicon bring-up.
Lead IP development, improve design methodology (including AI-assisted flows), and mentor engineers to deliver first-pass silicon success for NVMe and chiplet-based storage systems.
Experience Level
Senior level. The posting specifies 3–7 years of ASIC design experience as guidance for candidates.
Responsibilities
Primary responsibilities include IP design ownership, cross-functional coordination, and ensuring silicon readiness.
- Design and verify high-speed interface IP for next-generation storage subsystems (NVMe or chiplet architectures).
- Define micro-architecture and implement RTL using SystemVerilog/Verilog.
- Drive methodology and flow improvements, including AI-assisted design automation where applicable.
- Coordinate with firmware, software, and system teams from RTL development through silicon bring-up and validation.
- Lead timing closure, Clock Domain Crossing (CDC) mitigation, synthesis flows, and gate-level simulation activities.
- Mentor and guide engineers to achieve design quality and first-pass silicon success.
Requirements
Must-have technical skills are listed first; preferred skills follow.
- Must-have: Experience with SystemVerilog/Verilog for RTL development and micro-architecture definition.
- Must-have: ASIC design experience (posting indicates 3–7 years) with hands-on RTL debugging using Verdi/VCS.
- Must-have: Scripting/automation experience (Python or Perl) to support verification and flow automation.
- Must-have: Practical experience with CDC analysis, timing closure, synthesis flows, or gate-level simulation (GLS).
- Preferred: PCIe (Gen4/5/6) architecture knowledge (TLP/FLIT pipelines, flow control, ordering rules) and performance tuning.
- Preferred: Experience with link training, power states (L0/L0p/L1/L2), and error handling (AER).
- Preferred: Demonstrated cross-functional leadership interfacing with software/system teams during RTL-to-silicon cycles.
- Preferred: Familiarity with AI-assisted design flows is a plus.
Education Requirements
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
About the Company
Company: SK hynix America
U.S. subsidiary of SK hynix, a global semiconductor company specializing in DRAM and NAND flash memory and related memory solutions for mobile devices, data centers, and consumer electronics. Focuses on advanced memory technologies, AI applications, and high-performance storage.
