Sr. Staff Engineer, Hardware Design, Test Ops

Job Title

Senior Staff Engineer, Hardware Design — Test Ops

Role Summary

Lead hardware design review and development for high‑speed MLO and PCB probe card and ATE/load‑board hardware within Central Engineering. Focus on signal integrity, high‑speed layout, simulation, and cross‑team technical coordination to support wafer‑sort and SerDes test hardware.

Experience Level

Senior-level. The posting specifies degree-based experience minimums (Bachelor’s +9 years, Master’s +6 years, PhD +4 years); expect advanced technical leadership with roughly 7+ years of relevant engineering experience.

Responsibilities

Primary responsibilities include design review, simulation, and cross-functional support.

• Lead review and validation of MLO and PCB designs for probe cards and ATE/load boards.
• Perform signal‑integrity and power‑integrity simulations and interpret results for high‑speed serial and memory channels.
• Define and review layout guidelines: stack‑up, routing topology, via structures, and impedance control.
• Collaborate with test, package and board teams to identify and resolve electrical and mechanical issues affecting wafer‑sort hardware.
• Mentor engineers and contribute to design reviews, documentation, and technical decision making.

Requirements

Key technical must-haves and preferred skills.

• Must have: 5+ years designing high‑speed, high‑density PCBs or MLOs containing high‑speed serial and memory interfaces.
• Must have: 3+ years experience in signal‑integrity and power‑integrity simulation and analysis.
• Must have: Proficiency with industry simulation tools such as Keysight ADS, Cadence Sigrity, or Ansys HFSS.
• Must have: Practical knowledge of differential signaling, PAM4/NRZ channels, and RF/microwave concepts.
• Nice to have: Familiarity with ATE platforms (Advantest V93000, Teradyne UltraFLEX), probe card or load‑board design, and semiconductor ATE test hardware development.
• Nice to have: Experience evaluating PCIe, DDR3/4 and NAND topologies and performing high‑speed layout reviews.

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related technical field with at least 9 years of relevant experience; Master’s degree with at least 6 years; PhD with at least 4 years. Fields explicitly referenced: Computer Science and Electrical Engineering. No specific certifications were listed; equivalent experience was not stated.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.