Sr Staff Engineer, FE-DFT and Timing Closure

Job Title

Sr Staff Engineer, FE-DFT and Timing Closure

Role Summary

Senior front-end engineer responsible for bridging RTL/front-end design and DFT/back-end implementation. Lead development and deployment of DFT-aware front-end methodology for customer SoC programs and support R2G flow execution.

This is a customer-facing technical role that combines hands-on RTL debugging, methodology development, and cross-functional coordination to prevent and resolve DFT and timing closure issues.

Experience Level

Senior - 10+ years of hands-on front-end RTL design experience with significant exposure to DFT implementation and test methodology.

Responsibilities

Primary responsibilities focus on front-end DFT methodology, customer support, and cross-functional issue resolution.

• Lead front-end design and DFT methodology for customer SoC programs to ensure RTL supports robust scan insertion and R2G flows.
• Establish DFT-aware coding practices, hierarchy planning, clock architecture, and constraint definitions with front-end teams.
• Deploy and support DFT implementation flows including scan insertion, compression, ATPG, and boundary scan across programs.
• Act as the technical bridge between front-end designers and back-end DFT/implementation/verification teams.
• Debug complex failures tracing to RTL, tool interpretation, or constraint mismatches and drive cross-team resolution.
• Develop and standardize R2G flow methodologies integrating front-end quality checks with DFT readiness and implementation needs.
• Support risk mitigation and schedule recovery when front-end and DFT integration issues block program progress.

Requirements

Must-have technical skills and experience.

• 10+ years of hands-on front-end RTL design experience with substantial exposure to DFT implementation and test methodology.
• Strong understanding of DFT concepts: scan chains, compression, ATPG, boundary scan, and how RTL decisions affect test coverage and flow execution.
• Proven ability to debug cross-domain issues spanning front-end design, DFT insertion, and back-end implementation across multiple EDA tools.
• Experience developing or deploying R2G flows that integrate front-end design quality, DFT readiness, and back-end requirements.
• Ability to work across cross-functional teams and communicate technical issues clearly to both design and DFT engineers.
• Nice-to-have: experience working directly with customers or internal product teams in a technical lead or applications engineering capacity.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field - or equivalent practical experience in SoC design and DFT-related work.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.