Sr Staff Engineer - DFT
Marvell TechnologyJob Title
Sr Staff Engineer - DFT
Role Summary
Senior DFT engineer on the Optical DSP (ODSP) team responsible for defining DFT architecture and implementation for blocks inside advanced SoCs. Lead methodology, ATPG and test sign-off, silicon debug, and cross-functional coordination with design, verification, PD, and test.
The role focuses on establishing flows and automation for flagship ODSP programs developed in advanced process nodes.
Experience Level
Senior; expects experienced engineers with multi-year DFT practice and responsibility for architecture, sign-off, and mentoring.
Responsibilities
Primary responsibilities include DFT architecture, implementation, sign-off, silicon debug, and methodology improvement.
- Define block-level DFT architecture: hierarchical DFT, test modes, and clocking.
- Plan, partition, and integrate IP-level DFT for SerDes, PLLs, memories, and third-party IP.
- Drive ATPG coverage, test-time and pattern-count targets; optimize compression and power during test.
- Lead DFT sign-off: DRC, simulation, timing, equivalence, and handoff to PD/ATE.
- Debug silicon: failure isolation, diagnosis, and yield learning with Product/Test engineering.
- Mentor junior engineers and review their work; coordinate with design, verification, PD, and test teams.
- Improve DFT methodology and automation.
Requirements
Must-have technical skills and proven experience relevant to the role.
- Proven DFT experience on complex SoCs with multiple tape-outs and silicon bring-ups.
- Deep expertise in scan design, compression, ATPG fault models, MBIST and repair, JTAG, and at-speed test.
- Strong DFT timing and static timing analysis (STA) knowledge.
- Experience with advanced process nodes; 7nm and below preferred.
- Demonstrated independent problem solving and mentoring capability.
- Ability to coordinate across design, verification, PD, and test organizations.
- Nice-to-have: experience with high-speed SerDes and DSP products.
Education Requirements
BS in Electrical Engineering or Computer Engineering (posting specifies BS with ~8+ years DFT experience) or MS in Electrical Engineering or Computer Engineering (posting specifies MS with ~5+ years DFT experience). The posting also expects multiple tape-outs and silicon bring-ups.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
