Sr. Staff Engineer - DFT

Job Title

Sr. Staff Engineer - DFT

Role Summary

Design and implement Design-for-Testability (DFT) architectures and test infrastructure for ultra-low-power SoCs. Own DFT strategy and work cross-functionally with design, verification, physical design, and manufacturing/test teams to meet testability, yield, and quality targets.

This position is on-site five days a week in northwest Austin, TX.

Experience Level

Senior — typically requires 10+ years of DFT implementation experience.

Responsibilities

Key responsibilities include:

• Insert and validate scan, boundary scan, MBIST, and ATPG for low-power SoCs using standard EDA tools.
• Design and implement low-power DFT architecture and infrastructure, including scan compression and hierarchical DFT.
• Generate structural test vectors; analyze and improve coverage, test time, and test cost.
• Perform pre- and post-layout scan and MBIST simulations and develop ATPG/MBIST testbenches.
• Collaborate with designers on STA, physical, power, and logical issues affecting DFT.
• Work with test engineering to bring up test vectors and production test programs on silicon.

Requirements

Must-have and preferred technical skills:

• Must-have: 10+ years of hands-on DFT implementation experience for complex SoCs.
• Must-have: Hands-on expertise with Cadence Genus and Modus Compression for low-power scan insertion and ATPG pattern generation.
• Must-have: Strong knowledge of DFT methodologies: scan (stuck-at, at-speed, path-delay), scan compression, boundary scan, and MBIST.
• Must-have: Experience with hierarchical DFT architectures and memory test strategies; experience with Tessent MBIST flow and memory repair patterns.
• Must-have: Experience in test coverage analysis, test-time optimization, and ATE failure data diagnosis using ATPG tools.
• Experience developing ATPG and MBIST testbenches and performing pre-/post-layout simulations; gate-level simulation experience preferred.
• Solid understanding of timing analysis, constraint development, and RTL design/verification.
• Proficiency in Tcl; Perl and/or Python preferred.
• Strong problem-solving skills and effective verbal/written communication.
• Work authorization: candidates must be authorized to work in the U.S.; valid EAD and certain H-1B transfers may be considered. No new H-1B sponsorship available.

Education Requirements

BS or MS in Electrical Engineering, Electronics Engineering, or a related technical field. The role expects substantial practical experience (10+ years) in DFT implementation for complex SoCs.

About the Company

Company: Ambiq

Headquarters: Austin, TX, United States

Semiconductor company developing ultra-low-power microcontroller units (MCUs) and system-on-chip (SoC) platforms for battery-powered and edge devices, focusing on low-power IP, RTL, and production silicon solutions.