Sr. Staff Engineer - Design Verification
SiFiveJob Title
Sr. Staff Engineer - Design Verification
Role Summary
As a Senior Staff Hardware Engineer in Design Verification, you will own verification strategy and execution for complex SoC/IP blocks from architecture through tape-out. You will define methodology, lead test-plan creation, implement testbenches, and partner with architecture, RTL design, and validation teams.
This role provides technical leadership across projects, mentors engineers, and drives verification quality to achieve coverage and sign-off criteria.
Experience Level
Senior — typically 10+ years of ASIC/SoC/IP design verification experience with demonstrated staff-level impact.
Responsibilities
Lead verification activities and deliver verification sign-off for complex blocks and subsystems.
- Own verification strategy, methodology, and test plans for one or more complex subsystems (CPU, cache, LSU, interconnect, IP blocks).
- Architect and implement constrained-random, coverage-driven testbenches using SystemVerilog/UVM or equivalent.
- Develop reusable verification components: agents, monitors, scoreboards, checkers, and VIP integrations.
- Define and close functional, code, assertion, and scenario coverage; track metrics and sign-off criteria.
- Specify and implement assertions (SVA) and apply formal verification where appropriate.
- Lead bring-up and debug of complex functional and corner-case failures; collaborate with RTL designers to root-cause and propose fixes.
- Define and evolve DV methodology, CI/regression flows, and work with CAD/infra to improve automation and farm utilization.
- Mentor junior and mid-level engineers; review and sign off on test plans and environments.
- Participate in spec, micro-architecture, and tape-out sign-off reviews; coordinate with software and validation teams for end-to-end coverage.
Requirements
Must-have technical skills, domain knowledge, and soft skills for the role.
- Extensive hands-on experience with SystemVerilog and UVM or comparable class-based verification methodologies.
- Proven experience verifying complex CPU/SoC/IP blocks such as cache/memory subsystems, interconnects, accelerators, or I/O.
- Strong understanding of digital design: pipelines, coherency, memory hierarchy, clocking, resets, and CDC.
- Experience with coverage-driven verification, functional and code coverage, and assertion-based verification (SVA).
- Practical debug experience with tools like Verdi, DVE, SimVision and simulators such as VCS, Xcelium, or Questa and regression infrastructure.
- Knowledge of CPU microarchitecture (RISC-V/ARM/x86), cache coherence, memory protocols, on-chip interconnects, and protocols such as AXI or TileLink.
- Demonstrated technical leadership, mentoring ability, strong analytical skills, and clear verbal/written communication.
- Ability to pass background checks and confirm legal right to work in India; ability to obtain export-control authorization if required.
- Nice-to-have: formal verification, emulation/FPGA prototyping, low-power verification, and experience introducing new DV tools and flows.
Education Requirements
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
