Sr. Staff Engineer, ASIC Design

Job Title

Sr. Staff Engineer, ASIC Design

Role Summary

Design, bring up, and debug complex digital subsystems for electro-optical System-on-Chips used in high-performance AI data paths. Work on RTL, verification, silicon bring-up, and cross-disciplinary integration with analog, photonics, and firmware teams.

This role supports co-packaged optics (CPO) and high-speed interconnect work to improve data transfer performance and energy efficiency in next-generation AI systems.

Experience Level

Senior — typically 5+ years of ASIC design experience.

Responsibilities

Hands-on technical work across RTL design, verification, and silicon bring-up; collaborate with analog, photonics, and firmware engineers to deliver production-ready ASIC blocks.

• Develop digital algorithm specifications in collaboration with analog, photonics, and firmware teams.
• Implement and optimize RTL in Verilog/SystemVerilog for electro-optical ASICs.
• Create models and testbenches for digital and mixed-signal blocks and verify functionality.
• Prepare design documentation to support backend physical implementation and timing signoff.
• Bring up, evaluate, and debug custom silicon using Python scripting and firmware interfaces.
• Contribute to automated design methodologies and ASIC digital design flows.
• Work with high-speed interconnects and optical systems during design and bring-up.

Requirements

Must-have technical skills and proven hands-on ASIC delivery experience; items labelled as "nice-to-have" are optional but beneficial.

• Must-have: 5+ years of ASIC design experience with independent technical delivery.
• Must-have: Mastery of Verilog and SystemVerilog for RTL design and verification.
• Must-have: Experience with ASIC verification tools (XCelium, VCS, Questa).
• Must-have: Proficient in Python and low-level languages (C/C++).
• Must-have: Experience with ASIC synthesis tools (Genus, Design Compiler) and writing timing constraints.
• Must-have: Knowledge of digital timing, multiple clock domains, clock dividers, and standard ASIC tool flows.
• Must-have: Experience with silicon bring-up, debug, and evaluation; familiarity with SoC interconnects (AMBA AXI/AHB/APB).
• Nice-to-have: Experience with Cadence Virtuoso environment (schematic, layout, simulation), DFT methodologies (scan insertion, BIST, ATPG), high-speed SerDes, optics, or FPGA/microcontroller platforms.

Education Requirements

Bachelor of Science in Electrical Engineering, Computer Engineering, or a related technical field (BS in EE/CE or related).

About the Company

Company: Ayar Labs

Developer of co-packaged optics (CPO) that use light to move data at high speed with lower energy, targeting AI-scale interconnects. Their silicon photonics solutions aim to enable next-generation AI architectures and are backed by industry partners including NVIDIA, AMD, and Intel.