Sr. Staff Digital Verification Engineer - Memory Interface IP (HBM/DDR/LPDDR)
SynopsysJob Title
Sr. Staff Digital Verification Engineer - Memory Interface IP (HBM/DDR/LPDDR)
Role Summary
Lead verification engineer on the Interface IP team responsible for designing and executing verification strategies for memory interface IP (HBM, DDR, LPDDR and AMBA). The role focuses on building reusable verification environments, closing functional coverage, and working with design and architecture teams to ensure production-quality IP.
Experience Level
Senior - typically requires 6 to 8+ years of ASIC/SoC verification experience working on complex interface or memory IP.
Responsibilities
Hands-on responsibility for verification environments, test plans, and coverage-driven closure for memory interface IP.
- Design and build verification environments for HBM, DDR, LPDDR, and AMBA using SystemVerilog and UVM.
- Create detailed test plans covering functional scenarios, protocol compliance, and corner cases for memory controllers and interface IP.
- Develop reusable VIP and testbenches adaptable across projects and IP variants.
- Collaborate with design and architecture teams to identify bugs, clarify specs, and close coverage gaps before tapeout.
- Run functional coverage analysis, track metrics, and drive coverage closure across multi-protocol environments.
- Mentor and guide junior verification engineers on UVM best practices, debugging, and verification strategy.
- Use commercial simulators (VCS, ModelSim, Xcelium or equivalent) to execute regressions, debug failures, and validate fixes.
Requirements
Core technical skills and proven experience required for the role.
- Proven track record verifying Interface IP protocols (HBM, DDR, LPDDR, AMBA) in production-level designs.
- Strong proficiency in SystemVerilog and UVM, including building testbenches and assertions.
- Deep understanding of digital design, timing, protocol compliance, and memory subsystem architecture.
- Experience using simulators such as VCS, ModelSim, Xcelium, or equivalent in regression and debug workflows.
- Experience driving functional coverage closure and delivering verified IP on schedule.
- Demonstrated ability to mentor engineers and improve verification environments and methodologies.
Nice-to-have:
- Direct experience with HBM2/HBM3, DDR4/DDR5, or LPDDR4/LPDDR5 implementations.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. The posting specifies these degrees; no explicit mention of alternative equivalency or certifications was provided.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
