Sr Staff Digital Engineer

Job Title

Sr Staff Digital Engineer

Role Summary

Senior digital design engineer responsible for architecture, RTL development, SoC/subsystem integration, and silicon bring-up for mixed-signal and digital SoC products. Part of the Analog & Connectivity Business Group working with architecture, verification, DFT, physical design, firmware, and analog teams across product lifecycle.

Experience Level

Senior-level. Typically requires extensive industry experience (senior contributor with many years of hands-on ASIC/SoC development experience).

Responsibilities

Design, integrate, and deliver complex digital and mixed-signal SoC features from architecture through production release.

• Define digital architecture and micro-architecture for mixed-signal and SoC products.
• Develop high-quality RTL using Verilog/SystemVerilog and lead design reviews.
• Drive SoC and subsystem integration, including bus architectures and peripheral interfaces.
• Create and validate timing constraints, synthesis scripts, and implementation flows.
• Analyze and resolve CDC, RDC, lint, and timing issues to achieve design signoff.
• Collaborate with verification on test planning, coverage closure, and debugging.
• Support DFT implementation (scan, MBIST, JTAG) and production test methodologies.
• Work with physical design to meet power, performance, and area targets.
• Perform silicon bring-up, debug, characterization, and root-cause analysis.
• Document designs and contribute to future technology and architecture definitions.

Requirements

Core technical skills and hands-on experience required for the role.

• Strong background in digital IC and SoC architecture, design, and implementation.
• Proven experience with SoC interconnects and protocols (AHB, APB, AXI, USB, I2C/I3C, SPI, UART).
• Extensive RTL design experience with Verilog/SystemVerilog.
• Experience across the ASIC/SoC flow: RTL design & simulation, lint/design quality checks, CDC/RDC verification, logic synthesis, STA, and timing closure.
• Experience with DFT, SDC constraint development, and synthesis/implementation flows.
• Strong understanding of multi-clock designs, reset architecture, and low-power design methodologies.
• Experience driving technical debug and resolving functional, timing, and silicon issues during bring-up.
• Strong communication, problem-solving, and teamwork skills; self-starter.
• Familiarity with leveraging AI tools to improve engineering productivity and design quality.

Nice-to-have:

• Mixed-signal IC development and analog/digital integration experience.
• Hands-on experience with EDA tools (e.g., Synopsys Design Compiler, PrimeTime, SpyGlass, VC Static, Verdi, Cadence).
• Experience integrating/debugging Arm processor subsystems and firmware interactions (Cortex-M family or similar).
• High-speed interface design experience and FPGA prototyping/emulation familiarity.
• Mandarin proficiency is a plus for collaboration with teams in China.

Education Requirements

Posting specifies: MSEE or Ph.D. in Electrical Engineering with 8+ years of relevant industry experience, or BSEE with 12+ years of relevant industry experience.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.