Sr. Staff Design Verification Engineer
d-MatrixJob Title
Sr. Staff Design Verification Engineer
Role Summary
Senior verification engineer responsible for planning and executing SoC/IP verification from architecture through tape-out and silicon bring-up. You will work on a programmable in-memory computing architecture within a cross-functional hardware engineering team.
This role focuses on developing verification environments, driving coverage closure, and debugging complex verification failures in collaboration with design, architecture, and physical design teams.
Experience Level
Senior — expects extensive industry experience: typical guidance in this posting is 12+ years (or 7+ years with an MS).
Responsibilities
Primary responsibilities include planning and executing verification activities and improving verification methodology and infrastructure.
- Develop and execute verification plans across SoC/IP verification cycle from architecture to tape-out and bring-up.
- Build and maintain UVM/OVM-based verification environments for complex ASIC/SoC designs.
- Write and debug SystemVerilog testbenches using randomization, functional coverage, and assertions.
- Drive root-cause analysis and debug verification failures with design and architecture teams.
- Define and track coverage-closure goals to ensure verification sign-off.
- Align verification strategy with tape-out schedules through cross-functional partnership.
- Contribute to evolving verification methodology and infrastructure for next-generation architectures.
Requirements
Must-have technical skills and professional experience; preferred items listed separately.
- 12+ years of industry experience (role guidance; see Education Requirements for degree-specific guidance).
- Experience across full SoC/IP verification cycle, including tape-out and silicon bring-up.
- Hands-on test development and debug experience for ASIC/SoC verification.
- Fluency in SystemVerilog (randomization, constraints, coverage, assertions).
- Experience with verification methodologies such as UVM/OVM/VMM.
- Strong problem-solving and debugging skills for complex verification issues.
Nice-to-have:
- Experience with C/C++ and SystemC.
- Proven track record leading the creation and implementation of multiple SoC verification environments and driving tape-out efforts.
Education Requirements
Bachelor's degree in Electrical Engineering, Computer Science, or a related field is listed (BS with 12+ years). A Master's degree is preferred (MS with ~7+ years). The posting specifies degree types and the associated experience expectations; no explicit "or equivalent" substitution language is provided.
About the Company
Company: d-Matrix
Headquarters: Santa Clara, California, United States
d-Matrix is a Santa Clara–based startup developing highly programmable in-memory computing architectures and accompanying software to accelerate generative AI and other AI workloads, focusing on hardware-software co-design for cloud and edge applications.
