Sr Staff COE Verification Engineer

Job Title

Sr Staff COE Verification Engineer

Role Summary

Senior verification engineer in the Center of Excellence (COE) within Custom Compute and Storage, responsible for defining and delivering verification plans and reusable IP subsystem verification environments for PCIe/CXL and related interfaces. Work spans protocol-level verification, UVM/SystemVerilog testbench development, coverage closure, and cross-team collaboration with design, architecture, firmware, and validation.

Experience Level

Senior-level. 5–10 years of ASIC/SoC verification experience (as stated in the posting).

Responsibilities

Primary responsibilities include owning end-to-end verification, building scalable environments, and driving signoff for high-speed interfaces.

• Own verification planning and signoff for PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems.
• Architect and develop scalable UVM/SystemVerilog testbenches and integrate PCIe/CXL VIP.
• Create constrained-random and directed test suites, sequences, and checkers for functional and performance validation.
• Implement SystemVerilog Assertions and drive coverage-driven verification (functional, code, assertion) to closure.
• Perform protocol-level verification and debug protocol violations, ordering issues, and coherency bugs using simulators, waveforms, and protocol analyzers.
• Validate CXL.io, CXL.cache, and CXL.mem protocol behavior, coherency, and memory semantics.
• Measure and validate performance metrics (latency, throughput, QoS) under high-bandwidth and stress workloads.
• Develop automation (Python/Shell) for regression management, log triage, and coverage reporting.
• Support emulation/FPGA validation and contribute to post-silicon bring-up where applicable.
• Review design specifications for testability and mentor junior engineers on verification best practices.

Requirements

Must-have skills and experience; preferred items listed below.

• 5–10 years of ASIC/SoC verification experience focused on high-speed interfaces.
• Strong knowledge of PCIe and CXL protocols and architecture.
• Expertise in SystemVerilog and UVM methodology.
• Proven ability to debug complex verification issues using industry-standard simulation and waveform tools.
• Familiarity with industry-standard verification tools for simulation, coverage, and protocol analysis.
• Solid understanding of digital design fundamentals.

Nice-to-have:

• Experience with assertion-based verification (SVA).
• Exposure to emulation platforms (e.g., Palladium, Veloce) and post-silicon/FPGA bring-up.
• Performance modeling and traffic generation experience.
• Scripting skills: Python, Perl, or Shell.
• Experience with low-power verification flows (UPF).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field (as stated in the posting).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.