Staff RTL Design Engineer
Design and implement microarchitecture and RTL for RISC-V CPU cores within a cross-functional engineering team. Deliver production CPU IP and generator-based cores that meet performance, area, power, and quality targets.
Collaborate with verification, physical implementation, and performance teams to take features from specification through implementation and silicon readiness. Role is based in Hsinchu, Taiwan.
Senior β typically requires 5+ years of RTL design experience for CPU products.
Primary responsibilities include:
Must-have technical skills and attributes:
BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, or equivalent practical experience.
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
