Sr. Staff ASIC Verification Engineer

Job Title

Sr. Staff ASIC Verification Engineer

Role Summary

Senior verification engineer responsible for leading pre-silicon verification and post-silicon validation of Tensordyne's next-generation ASICs that integrate computational accelerators with 3rd-party SoC IP. The role partners with architecture and design teams to ensure functional correctness and performance from block level through full-chip tapeout.

Experience Level

Senior — requires extensive ASIC verification experience (senior-level, leadership on multiple tapeouts).

Responsibilities

Key responsibilities include verification planning, implementation, and signoff across block, subsystem, and full-chip levels.

• Lead all phases of ASIC verification for multi-million-gate SoCs integrating accelerators and 3rd-party IP.
• Define verification plans from architecture through tapeout and drive signoff criteria and quality metrics.
• Develop and scale block-level, subsystem, and full-chip verification environments and tests using SystemVerilog and UVM.
• Create constrained-random stimulus, functional coverage models, and drive coverage convergence.
• Verify embedded CPUs and interconnect subsystems (ARM/RISC-V), including C and assembly diagnostic validation.
• Debug and triage functional and performance issues; coordinate fixes with design and architecture teams.
• Manage bug tracking, regression runs, and verification closure activities.
• Mentor and provide technical guidance to verification engineers on test planning and closure.
• Develop scripts and front-end ASIC flow methodologies; perform diagnostic and post-silicon lab validation.

Requirements

Must-have technical skills and experience; items listed as "nice-to-have" are explicitly noted.

• Must-have: 15+ years of ASIC verification experience with multiple chips taken through verification and post-silicon validation.
• Must-have: Expert in SystemVerilog, UVM, constrained-random verification, and functional coverage-driven methodologies.
• Must-have: Experience with C/C++ or SystemC for verification tasks.
• Must-have: Verification experience with high-speed interfaces such as PCIe, Ethernet, DDR/HBM, SerDes.
• Must-have: Strong debugging skills and experience handling bug tracking, regression failures, and coverage convergence.
• Must-have: Experience performing post-silicon validation and lab diagnostics.
• Nice-to-have: Scripting experience in Python, Perl, Tcl, or shell to automate flows and tests.
• Nice-to-have: Interest or experience with AI architectures (convolution, transformer workloads) and accelerator verification.

Education Requirements

B.S. degree required; M.S. preferred — in Electrical Engineering, Computer Engineering, Computer Science, or a similar technical field (as stated).

About the Company

Company: Tensordyne

Tensordyne is a startup developing high-performance, low-power AI inference processors and multi-chip systems for generative AI acceleration in data centers. The company focuses on ASIC design, verification, and integration of computational accelerators with third-party SoC IP.