Sr. Staff ASIC Verification Engineer

Job Title

Sr. Staff ASIC Verification Engineer

Role Summary

Lead pre-silicon verification for next-generation multi-million-gate ASICs that integrate accelerator cores with 3rd-party SoC IP. Responsible for verification planning, development of block-to-full-chip test environments, driving coverage convergence and signoff, and supporting post-silicon validation. This is a remote role working with teams across San Jose and Munich.

Experience Level

Senior-level. The role expects extensive senior ASIC verification experience (see Requirements); the posting specifies approximately 15+ years of relevant experience.

Responsibilities

Primary responsibilities include:

• Lead verification planning from architecture through tapeout: define test plans, signoff criteria, and quality metrics.
• Design and implement block-level, subsystem, and full-chip verification environments and tests using object-oriented methodologies (SystemVerilog/UVM).
• Develop constrained-random stimulus, functional coverage models, and coverage-driven verification strategies; drive coverage convergence.
• Verify SoC subsystems including embedded CPUs (ARM/RISC-V), interconnects, and high-speed interfaces (PCIe, Ethernet, DDR/HBM, SerDes).
• Collaborate with design and architecture teams to clarify specifications, diagnose functional and performance issues, and iterate on fixes.
• Manage bug tracking, regression failures, and verification closure activities.
• Mentor and technically guide verification engineers; establish reusable methodologies and scaleable testbench frameworks.
• Develop scripts and methodologies for front-end ASIC flows and perform diagnostic and post-silicon lab validation when required.

Requirements

Must-have and preferred technical skills:

• Must-have: 15+ years of ASIC verification experience with ownership of multiple chips through verification and post-silicon validation; expert knowledge of SystemVerilog, UVM, constrained-random stimulus, and functional coverage; strong C/C++ or SystemC experience; deep understanding of object-oriented programming principles; verification experience with high-speed interfaces (PCIe, Ethernet, DDR/HBM, SerDes).
• Preferred: Scripting skills (Python, Perl, TCL, shell); experience with embedded CPU/SoC verification and interconnect subsystems; familiarity with front-end ASIC flows and post-silicon debug; interest in AI accelerator architectures (convolution, transformer workloads).
• Behavioral: Self-starter comfortable in a fast-paced startup, able to lead teams and mentor engineers toward verification closure.

Education Requirements

Bachelor of Science in Electrical Engineering or Computer Engineering (B.S.). Master’s degree preferred (M.S.). The posting references degrees in Electrical or Computer Engineering or a similar field; no specific certifications were listed. Equivalent practical experience is not explicitly stated but may be considered in lieu of an advanced degree.

About the Company

Company: Recogni

Headquarters: San Diego, California, United States

Recogni is a cutting-edge AI solution company specializing in high-performance, low-power AI inferencing designed for various industries. The company focuses on multimodal AI inference acceleration and is dedicated to advancing research and product developments in AI technologies. Based in San Diego, California, and Munich, Germany, Recogni values employee well-being and offers competitive benefits and a dynamic startup environment.