Senior LPU ASIC Engineer

Job Title

Senior LPU ASIC Engineer

Role Summary

Lead physical implementation and optimization for NVIDIA's LPU chip, owning block- and top-level synthesis, floorplanning, place & route, timing closure, UPF-based low-power flows, and sign-off activities. Collaborate with IP, front-end logic, architecture, CAD, and sign-off teams to deliver tapeouts for advanced-node, high-performance SoCs.

Base salary range: 136,000 USD - 218,500 USD (Level 3) and 168,000 USD - 264,500 USD (Level 4). Employees may also be eligible for equity and benefits.

Experience Level

Senior-level. Typically requires 5+ years of industry experience delivering full-flow physical design for large-scale, high-performance SoCs at advanced process nodes.

Responsibilities

Primary responsibilities include leading physical implementation, cross-functional optimization, and tapeout execution.

• Own full-flow physical implementation at block/partition and top level: synthesis, floorplan, placement, CTS, routing, extraction, and timing sign-off.
• Define and enforce timing constraints, UPF low-power intent, and formal equivalency check (LEC) strategies.
• Partner with IP, front-end logic, and architecture teams to integrate IP, remove architectural bottlenecks, and improve PPA.
• Lead design closure and tapeout readiness, coordinating with PnR, sign-off, verification, and manufacturing teams to ensure GDSII handoff.
• Develop and deploy data-driven, automated EDA flows and methodologies to improve PPA and cycle time.

Requirements

Must-have technical skills and experience for immediate contribution.

• Industry experience: 5+ years driving physical design through RTL-to-GDSII for large, high-performance SoCs at advanced nodes.
• Full-flow execution: Hands-on experience with synthesis, placement, CTS, routing, extraction, and physical/electrical verification.
• Low-power design: Deep knowledge of UPF/CPF flows, multi-voltage domain implementation, and rule verification; formal equivalence (LEC) experience.
• Clock & timing: Expert in advanced CTS methodologies and sign-off timing analysis (MCMM STA) with complex constraints.
• PPA & sign-off: Proven track record of aggressive power/performance/area optimization, power grid design, EMIR analysis, and ECO generation.
• DFT & integration: Experience optimizing DFT structures and handling block-level integration for physical implementation.
• EDA tools & automation: Expert-level proficiency with industry physical-design toolflows and strong scripting skills (TCL, Python, Perl) to automate flows and integrate AI-driven enhancements.
• Nice-to-have: Experience with high-speed SerDes IP (PCIe, CXL, C2C, die-to-die interfaces) and AI-assisted EDA optimizations.

Education Requirements

B.S. in Electrical Engineering, Computer Engineering, or a related technical field is expected, or equivalent practical experience. M.S. or Ph.D. is preferred. The posting explicitly allows equivalent experience in lieu of a degree.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.