Sr. Staff ASIC Design Verification Engineer
RivianJob Title
Sr. Staff ASIC Design Verification Engineer
Role Summary
Senior verification engineer responsible for end-to-end functional and performance verification of next-generation AI accelerator SoCs on the ADAS and Inference Silicon team. Work spans microarchitecture verification, coverage-driven verification, formal checks, and hardware-software co-verification for production-scale CNN and Transformer workloads.
Salary range for Palo Alto-based applicants: $237,000 - $296,000 (base).
Experience Level
Senior — typically 10+ years of industry experience in ASIC design verification; demonstrated experience taking multiple chips from concept to tape-out.
Responsibilities
Primary responsibilities include verification planning, execution, and collaboration across hardware and firmware teams.
- Lead end-to-end functional and performance verification for AI accelerator architectures; ensure numerical accuracy and high-bandwidth dataflow for production CNN and Transformer workloads.
- Develop and execute coverage-driven verification using SystemVerilog and UVM to meet aggressive functional targets.
- Apply formal verification (SVA) to exhaustively prove corner cases in safety-critical arbiters, state machines, and concurrency logic.
- Define and run fault-injection and safety validation strategies for ECC, parity, and BIST mechanisms (safety-critical work noted as nice-to-have).
- Collaborate with firmware and software teams on emulation and FPGA prototyping for hardware-software co-verification and full-stack validation.
- Mentor junior engineers and contribute to verification methodology and toolchain improvements.
Requirements
Must-have technical skills and proven experience to perform the role.
- 10+ years in ASIC design verification with hands-on experience across multiple chips to tape-out.
- Strong SystemVerilog and UVM experience for coverage-driven verification.
- Experience with formal verification using SVA.
- Deep understanding of computer architecture, memory hierarchies (cache, DMA, DDR/HBM), and interconnect protocols (NoC).
- Experience with low-power verification flows (UPF/CPF).
- Proven ability to develop verification plans and measure coverage/quality metrics.
- Nice-to-have: experience with systolic arrays, vector processors, NPUs, mapping CNN/Transformer workloads to hardware, compilers/toolchains, ISO 26262 safety verification, fault injection analysis, and LLM-augmented front-end workflows.
Education Requirements
BS, MS, or PhD in Electrical Engineering or Computer Engineering (or equivalent technical degree). Specific degree levels listed in the source are BS/MS/PhD in EE or CE.
About the Company
Company: Rivian
Headquarters: Irvine, CA, United States
Electric vehicle manufacturer focused on adventure-oriented, emissions-free trucks and SUVs, battery systems, charging infrastructure, and vehicle software. The company develops hardware and software for sustainable transportation, including advanced driver-assistance and infotainment systems.
