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Sr Staff Analog Layout Engineer

Marvell Technology
July 21, 2026
Full-time
On-site
San Diego, California, United States
$129,100 - $191,030 USD yearly
Physical Design Jobs, Level - Senior

Job Title

Sr Staff Analog Layout Engineer

Role Summary

Senior analog layout engineer on Marvell Central Engineering AMS-IP team responsible for creating and verifying high-speed SerDes and other analog mixed-signal layouts. The role supports lab validation and SoC production across Marvell products and works within the San Diego design organization.

Experience Level

Senior (Sr Staff). The posting provides experience guidance: typically 4–7 years with a Bachelor’s degree or 2–4 years with a Master’s/PhD, though the title and responsibilities indicate a senior-level role.

Responsibilities

Primary responsibilities include custom analog layout, verification, and collaboration with circuit designers to meet project specifications and timelines.

  • Design and optimize analog mixed-signal layouts (RX, TX, PLL and related blocks).
  • Floorplanning and full-custom layout implementation to schematic specifications.
  • Perform layout verification and fixes: DRC, LVS, ANT, LUP, ESD, PERC and ERC checks.
  • Work closely with circuit designers, validation, and cross-functional teams to meet project schedules.
  • Maintain detailed documentation of layout methodology, design decisions, and verification results.
  • Mentor and guide junior layout engineers.

Requirements

Must-have technical skills and experience for successful performance in this role.

  • Proficiency with custom-layout CAD tools such as Cadence Virtuoso (preferred); experience with Mentor Graphics or Synopsys Custom Compiler acceptable.
  • Familiarity with LVS, DRC, ERC, antenna rules, EM/IR analysis, ESD, and layout parasitic extraction (PERC/LUP).
  • Experience with FinFET processes and mixed-signal layout constraints.
  • Strong communication skills and ability to collaborate across engineering teams.
  • Demonstrated ability to mentor junior engineers and provide technical leadership in layout tasks.
  • Nice-to-have: experience with advanced TSMC process nodes (5nm, 3nm, 2nm).

Education Requirements

Options listed in the posting: Bachelor’s degree in Computer Science, Electrical Engineering, or a related field (with 4–7 years of relevant experience); or a Master’s degree or PhD in Computer Science, Electrical Engineering, or a related field (with 2–4 years of relevant experience). No certifications were specified. Equivalent-experience language was not provided.


About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.

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Date Posted: 2026-07-18