Sr Staff Analog Layout Engineer
Senior analog layout engineer on Marvell Central Engineering AMS-IP team responsible for creating and verifying high-speed SerDes and other analog mixed-signal layouts. The role supports lab validation and SoC production across Marvell products and works within the San Diego design organization.
Senior (Sr Staff). The posting provides experience guidance: typically 4–7 years with a Bachelor’s degree or 2–4 years with a Master’s/PhD, though the title and responsibilities indicate a senior-level role.
Primary responsibilities include custom analog layout, verification, and collaboration with circuit designers to meet project specifications and timelines.
Must-have technical skills and experience for successful performance in this role.
Options listed in the posting: Bachelor’s degree in Computer Science, Electrical Engineering, or a related field (with 4–7 years of relevant experience); or a Master’s degree or PhD in Computer Science, Electrical Engineering, or a related field (with 2–4 years of relevant experience). No certifications were specified. Equivalent-experience language was not provided.
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
