Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
SpaceXJob Title
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Role Summary
Design and implement next-generation ASICs for Starlink, focusing on RTL-to-GDSII physical implementation, signoff, and flow automation. Collaborate with systems, firmware, architecture, validation, and product engineering teams to deliver production silicon for space and ground infrastructure.
Work directly on timing, power, area, and manufacturability targets that improve the performance and reliability of the Starlink network.
Experience Level
Senior — 5+ years of industry experience in ASIC and/or physical design flow development, including implementation and signoff.
Responsibilities
Primary responsibilities include implementation, signoff, and flow development:
- Perform partition, synthesis, and full physical implementation steps: synthesis, floorplanning, power/ground grid generation, place & route, timing and noise analysis, physical verification, electromigration and IR drop analysis, logic equivalency and other signoff checks.
- Develop and improve physical design methodologies and automation scripts for implementation and signoff steps.
- Collaborate with ASIC design and architecture teams to define timing, power, and area targets and evaluate RTL/design trade-offs.
- Identify, debug, and resolve design, timing, and congestion issues; propose and drive execution of fixes.
- Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop analyses.
Requirements
Must-have and preferred technical qualifications (degree requirements are summarized below in Education Requirements).
Must-have- Strong experience in ASIC/SOC RTL-to-GDSII physical design and signoff flows and with industry-standard EDA tools.
- Understanding of CMOS digital design, standard cell libraries, and power dissipation in deep submicron processes.
- Knowledge of DFT (scan/MBIST/LBIST) and its impact on physical design flows.
- Proficient scripting skills (bash/csh, Perl, Python, TCL, Makefiles) for automation and flow development.
- Ability to work extended hours and weekends as needed to meet critical project milestones.
- ITAR eligibility: must be a U.S. citizen, U.S. national, lawful permanent resident, refugee, asylee, or otherwise eligible for required U.S. Department of State authorizations.
- Familiarity with FinFET / advanced CMOS device physics and analog physical design.
- Experience with timing/noise/IR/EM signoff at advanced nodes and flow optimization.
- Prior experience with space-qualified or high-reliability ASICs.
Education Requirements
Bachelor's degree in electrical engineering, computer engineering, or computer science (specified in the posting).
About the Company
Company: SpaceX
Headquarters: Hawthorne, California, United States
SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.
