Sr. Principal VLSI/ ASIC Design Engineer

Job Title

Sr. Principal VLSI/ ASIC Design Engineer

Role Summary

The Sr. Principal VLSI/ASIC Design Engineer will define architecture and lead RTL design and implementation for complex VLSI components and system-on-chip (SoC) solutions across networking, compute, and related products. This role provides technical leadership, drives architectural decisions, and mentors engineering teams.

Position is hybrid with an expected average of 2 days per week onsite at an HPE office in Sunnyvale, CA.

Experience Level

Senior-level. Typically requires 11+ years of experience in ASIC, VLSI, SoC, or related hardware design.

Responsibilities

Lead and deliver architecture and detailed RTL implementations, collaborate across functions, and provide technical leadership.

• Lead early-stage ASIC architecture and microarchitecture exploration for networking, compute, and SoC applications.
• Define design methodologies, implementation plans, and roadmap-aligned architecture choices.
• Design, develop, and modify complex RTL blocks using industry-standard HDLs.
• Drive RTL through synthesis, physical implementation support, timing closure, and production readiness.
• Analyze tradeoffs involving performance, power, area, scalability, reliability, and schedule.
• Develop models, run simulations, prototype, and evaluate performance and reliability metrics.
• Conduct design reviews and enforce architecture and implementation quality standards.
• Integrate new IP, tools, and methodologies into existing architectures and processes.
• Collaborate with architecture, hardware, firmware, verification, physical design, systems, software, manufacturing, and external partners.
• Mentor engineers, provide technical direction, and promote knowledge sharing and engineering excellence.

Requirements

Technical must-haves for successful performance in this role; preferred items listed separately.

• Must-have: Advanced knowledge of ASIC/VLSI design principles, digital logic, RTL design, and SoC development.
• Proven experience developing complex RTL using Verilog, SystemVerilog, or comparable HDLs.
• Practical experience with ASIC development flows: RTL coding, synthesis, timing analysis, and interaction with physical design teams toward signoff.
• Experience with design modeling, simulation, performance analysis, and empirical evaluation.
• Strong analytical and technical decision-making skills; ability to evaluate alternatives and recommend tradeoffs.
• Experience defining or improving design methodologies, automation, and engineering practices.
• Demonstrated ability to influence cross-functional and senior stakeholders and to work across geographically distributed teams.

Nice-to-have:

• Experience with networking ASICs, DPUs, switching/routing, packet-processing pipelines, or HPC architectures.
• Familiarity with formal/constrained-random verification, coverage methodologies, low-power design, CDC/CDC handling, DFT, and design-for-reuse.
• Experience working with IP vendors, foundries, or outsourced development partners.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent practical experience may be considered.

About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.