Sr Principal Verification Engineer

Job Title

Sr Principal Verification Engineer

Role Summary

Lead design verification for complex digital SoCs and subsystems, owning verification strategy, architecture, methodology, and delivery across multifunctional teams.

Work on next-generation intelligent-edge products, drive pre-silicon readiness (emulation/FPGA/software), and influence verification practices across business units.

Experience Level

Senior — typically 20+ years of experience in digital pre-silicon verification and technical leadership.

Responsibilities

Accountable for end-to-end verification planning and execution, mentoring, and cross-functional alignment.

• Lead end-to-end SoC/subsystem verification from planning through signoff.
• Define verification architecture, flows, methodology, and scalable UVM-based testbenches.
• Plan and track team tasks, provide technical leadership and mentoring.
• Collaborate with architecture, design, emulation, FPGA, firmware, and software teams to align verification deliverables and post-silicon scenarios.
• Develop and execute system-level use cases for functional validation and performance analysis.
• Drive verification closure using functional and code coverage across block, subsystem, and SoC levels.
• Apply formal verification techniques and lead NoC/interconnect verification.
• Support power-aware verification and integration with power analysis tools (UPF).
• Contribute to verification innovation, cross-company technical initiatives, and potential patent/publication efforts.

Requirements

Key technical and leadership requirements; degrees summarized separately under Education Requirements.

• 20+ years of experience in digital pre-silicon verification with leadership across IP, subsystem, or SoC DV.
• Expert in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation.
• Proven record of verification closure using functional and code coverage at block, subsystem, and SoC levels.
• Deep expertise in NoC, bus, and interconnect verification; coverage analysis and optimization.
• Experience with power-aware verification (UPF), formal verification, and gate-level simulation with timing annotation (GLS).
• Protocol verification experience (I2C, SPI, Ethernet, UART, AXI/AHB, DMA, SVI3) and system-level validation.
• Familiarity with processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators; proficiency in C/C++, SystemC, and scripting (Python/Tcl/Shell).
• Experience in security and safety verification and ability to ensure compliance with secure design and functional safety requirements.
• Excellent communication, leadership, and cross-functional collaboration skills; strong problem-solving and rapid learning capability.
• Nice-to-have: exposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY).
• Willingness to travel (~10%).
• Note: role may require export-licensing review for applicants who are not US citizens, US permanent residents, or other protected individuals.

Education Requirements

Requires a B.Tech or M.Tech degree (engineering) as stated in the posting. The posting specifies 20+ years of relevant experience; specific fields of study were not detailed.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.