Sr Principal SI/PI Engineer
Hands-on senior engineer in the HPP IP R&D Group responsible for signal integrity (SI) and power integrity (PI) for advanced high-speed IP products. The role focuses on test-chip and board-level SI/PI optimization, providing channel models, verifying link performance, and supporting customers and internal ASIC teams.
Works closely with package/PCB designers, lab engineers, and customers to ensure IP performs reliably in target systems.
Senior β typically 3+ years of relevant experience; the role is at a senior/principal level.
Key responsibilities include design, analysis, verification, and customer support for SI/PI of test chips, packages, and PCBs.
Must-have technical skills and experience.
M.S. or Ph.D. in Electrical Engineering or a related field (the posting specifies an MS or PhD in Electrical Engineering or similar degree).
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
