Sr. Principal Product Engineer — Silicon Signoff Verification (SSV), Digital Implementation & Signoff Solutions

Job Title

Sr. Principal Product Engineer — Silicon Signoff Verification (SSV), Digital Implementation & Signoff Solutions

Role Summary

Lead development and deployment of advanced signoff methodologies and customer enablement for timing signoff, ECO closure, power, and signal integrity across digital implementation and signoff solutions.

Work closely with customers, field teams, and R&D to resolve complex design-closure issues, qualify advanced-node flows, and influence product direction through hands-on methodology development and technical leadership.

Experience Level

Senior — 8–12+ years of industry experience in semiconductor design, physical implementation, timing signoff, or product engineering.

Responsibilities

Deliver methodology, customer support, and product enablement for signoff and ECO flows.

• Develop and deploy signoff methodologies covering timing, power, signal integrity, and ECO closure.
• Collaborate with customers, applications/field engineering, and R&D to resolve complex design-closure challenges and support tapeouts.
• Lead qualification and certification of advanced-node design flows and drive signoff correlation across implementation, STA, SPICE, and signoff environments.
• Develop and optimize multi-mode multi-corner (MMMC) timing closure and statistical timing approaches.
• Define and validate methodologies for setup/hold closure, power optimization, crosstalk mitigation, glitch fixing, max transition/electrical rule fixes, and multi-view timing closure.
• Perform root-cause analysis, debug critical project milestones, and lead technical investigations.
• Create deployment collateral, technical presentations, and best-practice guides to enable customer adoption.
• Drive adoption of emerging technologies including AI-assisted signoff and ECO automation.
• Mentor engineers, lead technical reviews, and manage customer escalations.

Requirements

Core technical skills and proven customer-facing experience required for the role.

• Must-have: 8+ years industry experience supporting advanced-node SoC/ASIC designs through implementation, timing closure, ECO convergence, and tapeout.
• Must-have: Deep expertise in Static Timing Analysis (STA), multi-mode multi-corner (MMMC) timing analysis, statistical timing, and signoff methodologies.
• Must-have: Strong skills in ECO implementation and closure flows; timing correlation and SPICE correlation; RC extraction and parasitic analysis.
• Must-have: Signal integrity and crosstalk analysis, glitch analysis and fixing, power optimization techniques, and physical implementation/signoff optimization.
• Must-have: Proven ability to lead root-cause analysis, drive product enhancements, and own strategic customer engagements.

Additional desirable qualifications.

• Nice-to-have: Experience with Cadence tools (Tempus, PrimeTime, Innovus/ICC/FC, Tempus ECO/Tweaker) and physical signoff environments.
• Nice-to-have: Experience with advanced-node technologies (7nm, 5nm, 3nm, 2nm+), large SoC designs (>100M instances), and foundry qualification programs.
• Nice-to-have: Exposure to AI-assisted implementation and signoff workflows and ECO automation.

Education Requirements

Not specified.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.