Sr. Principal Product Engineer

Job Title

Sr. Principal Product Engineer

Role Summary

Technical leader on the Voltus product engineering team responsible for power-noise, IR/EM, PDN and electrothermal signoff solutions. Acts as the primary technical interface among strategic customers/foundries, Applications, and R&D to convert signoff requirements into product features and validated flows.

Experience Level

Senior - minimum experience varies by degree: B.S. +10 years; M.S. +8 years; Ph.D. +6 years (per minimum qualifications).

Responsibilities

Primary responsibilities include defining product and flow solutions for advanced-node power integrity and signoff, leading enablement and qualification efforts, and resolving complex customer issues.

• Serve as the primary technical interface to R&D for Voltus; drive product requirements, priorities, and methodology for foundry and customer programs.
• Lead enablement for advanced-node IR/EM signoff: flow/techfile/PDK readiness, reference flows, qualification, benchmarking, and production deployment.
• Own resolution of complex issues across static/dynamic IR, EM, low-power and multi-voltage domains, hierarchical and full-chip signoff, and timing/stack-die interactions.
• Define and validate foundry-aligned power-integrity and EM modeling assumptions; partner with PDK, extraction, and signoff teams for advanced-node and 3DIC readiness.
• Influence product roadmap (including AI-driven IR mitigation, 3DIC, and electrothermal co-analysis) based on foundry and customer needs.
• Mentor Lead/Principal PEs and AEs; establish debug standards, deployment practices, and issue-tracking discipline for account/foundry programs.
• Collaborate with customers, field, Marketing, and R&D across geographies; present findings and recommendations to customer and internal leadership.

Requirements

Must-have technical skills and experience.

• Deep hands-on experience with industry-standard IR/EM (EMIR) and PDN analysis tools and digital physical implementation/signoff flows.
• Strong background in CMOS/digital design, power IR-drop analysis, and circuit analysis for low-power/multi-power-domain signoff.
• Proven ability to debug large SoC/PDN problems and drive resolution from customer requirement through R&D to deployment.
• Proficiency scripting in Tcl and Python.
• Strong written, verbal, and presentation skills for customer and executive audiences.

Nice-to-have:

• Direct experience with Voltus and adjacent Cadence tools (Integrity, Tempus, Innovus, Quantus/QRC).
• Experience with 3DIC/chiplet, electrothermal analysis, and advanced FinFET or GAA nodes.
• Prior technical leadership of PE/AE teams or strategic account/foundry programs.

Education Requirements

Bachelor’s in Electrical, Electronics, or VLSI Engineering with 10+ years relevant experience; or Master’s with 8+ years; or PhD with 6+ years. Degrees in closely related electrical or technical fields are indicated; no certifications are specified.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.