Sr Principal Engineer - SoC / Chip Lead

Job Title

Sr Principal Engineer - SoC / Chip Lead

Role Summary

Lead technical execution of complex SoC programs from architecture through silicon production. Coordinate cross-functional teams to define chip-level architecture, integration strategy, schedules, risk mitigation and ensure first-pass silicon success.

Provide technical leadership and mentorship across engineering organizations and drive cross-domain trade-offs and decision-making.

Experience Level

Senior — posting specifies 20+ years of semiconductor industry experience.

Responsibilities

Primary responsibilities include end-to-end leadership, planning, integration, and execution of SoC projects.

• Lead end-to-end SoC program execution from architecture to silicon production and productization.
• Define chip-level architecture, integration requirements, performance, power, and area targets.
• Plan and track schedules, manage technical dependencies and risks to tape-out readiness.
• Coordinate cross-functional teams: RTL design, verification, physical design, DFT, firmware, validation, packaging, and product engineering.
• Drive technical decision-making and trade-off analysis across architecture, implementation, and product requirements.
• Oversee subsystem and IP integration, including mixed-signal and high-speed interfaces.
• Lead design reviews, silicon readiness assessments, post-silicon debug, and issue resolution.
• Mentor senior engineers and provide technical leadership across multiple engineering groups.

Requirements

Minimum qualifications and required skills.

• 20+ years semiconductor industry experience with substantial leadership responsibility.
• Proven experience as Chip Lead, SoC Lead, Technical Program Lead, or equivalent for large-scale ASIC/SoC products.
• Demonstrated success leading advanced-node SoCs (experience with 3nm and/or 5nm preferred).
• Deep understanding of SoC architecture, integration methodologies, and full-chip development flows.
• Hands-on experience across RTL design, design verification, physical design, DFT, static timing analysis, low-power methodologies, silicon bring-up, and productization.
• Experience managing complex schedules, technical dependencies, and global cross-functional execution.
• Strong communication, stakeholder management, and engineering leadership skills.

Nice-to-have:

• Experience with high-performance switching silicon, NoC architectures, interconnect fabrics, HBM-centric systems, or chiplet architectures.
• Hands-on integration of high-speed SerDes, analog front-ends, mixed-signal IPs, advanced PHYs, and packaging/signal-integrity work.
• Experience in AI, HPC, networking, data-center, or memory-infrastructure products; familiarity with UALink, Ethernet switching, or switch fabrics.

Education Requirements

Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related discipline. Equivalent practical experience is acknowledged in the posting.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.