Sr. Principal Digital Designer

Job Title

Sr. Principal Digital Designer

Role Summary

The Sr. Principal Digital Designer will lead the architecture, implementation, and integration of digital subsystems for Automotive Ethernet PHY products (10BASE-T1S, 100BASE-T1, 1000BASE-T1, and multi-gig automotive SerDes). The role spans digital micro-architecture, RTL implementation, protocol logic, and system-level integration with mixed-signal and firmware teams.

The position owns end-to-end digital design decisions, drives feasibility and trade-off analyses, and supports validation, compliance, and production bring-up for automotive PHY devices.

Experience Level

Senior — typically requires 12+ years of experience in digital design for PHYs, SerDes, networking ASICs, or communication ICs.

Responsibilities

Primary responsibilities include defining architectures, delivering RTL, and owning system-level digital behavior for automotive PHY products.

• Define and own digital subsystem micro-architecture: PCS pipelines, encoding/decoding, scramblers/descramblers, CRC engines, framing, packet processing, link monitoring, and interface logic (MII/RMII/RGMII/GMII/XGMII).
• Perform system-level partitioning between digital, analog/mixed-signal, and firmware; lead feasibility studies and power/performance trade-offs.
• Develop high-quality RTL (Verilog/SystemVerilog) for control, datapath, and protocol logic; provide synthesis guidance and timing optimization.
• Drive digital front-end flows: linting, CDC/RDC mitigation, reset architecture, STA, and timing constraints.
• Collaborate with DV to define coverage goals, corner cases, and verification plans; support pre- and post-silicon validation and bring-up.
• Define control interfaces to analog front-end blocks, calibration engines, and register programming flows; contribute to compliance testing and system validation.
• Ensure automotive-quality and functional-safety implementation: safety mechanisms, diagnostics, watchdogs, FMEDA and functional safety analysis participation.
• Mentor and guide junior engineers; partner with firmware, PD, validation, and compliance teams to drive implementation and debug efforts.

Requirements

Must-have technical skills and experience for the role.

• 12+ years of digital design experience for PHYs, SerDes, networking ASICs, or communication ICs.
• Expertise in Verilog/SystemVerilog RTL design for control and datapath logic.
• Strong knowledge of high-speed digital logic, state machines, and control logic.
• Experience with IEEE 802.3 Ethernet PCS, link training, and system control flows.
• Practical experience with synthesis, static timing analysis (STA), and CDC/RDC methodologies.
• Proven track record of multiple production tape-outs and silicon bring-up.
• Preferred: experience with Automotive Ethernet standards (10BASE-T1S, 100BASE-T1, 1000BASE-T1, 10GBASE-T1), firmware-driven PHY initialization, post-silicon debugging tools, and safety-critical digital design background.
• Soft skills: technical leadership, mentoring, clear cross-disciplinary communication, and strong documentation practices.

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.