Sr Principal Design Engineer

Job Title

Sr Principal Design Engineer

Role Summary

Senior technical role on the North America Palladium and Protium HW Development team responsible for customer-facing system-level chip design verification and deployment of hardware emulation and FPGA prototyping platforms.

The role works with customers, Applications Engineering, Product Engineering, and R&D to develop solutions, provide deep technical support, and define verification methodologies for high-speed protocol and architectural challenges.

Experience Level

Senior — requires significant industry experience. Posting specifies: BS with a minimum of 10 years' relevant experience, or MS with a minimum of 7 years' relevant experience.

Responsibilities

Key responsibilities include technical leadership, customer enablement, and solution delivery for emulation and prototyping platforms.

• Collaborate with customers and frontline engineering teams to develop, deploy, and optimize protocol solutions on Palladium and Protium platforms.
• Define and develop emulation and prototyping requirements for leading-edge high-speed interfaces and memory protocols.
• Design and drive advanced acceleration firmware and FPGA system solutions; establish verification methodologies.
• Provide deep R&D technical support and bridge work between hardware and software teams.
• Triage and resolve complex hardware/software interaction issues; perform root-cause analysis and system stability improvements.
• Lead technical evaluations and develop benchmarks to demonstrate platform performance.
• Create and deliver technical presentations, white papers, and product demonstrations for customers and prospects.

Requirements

Must-have technical skills and experience.

• Strong fundamentals in digital design, computer architecture, and system-level verification.
• Hands-on experience with emulation, FPGA prototyping, and advanced simulation/testbench techniques.
• Proficiency with hardware description languages (SystemVerilog/Verilog) and/or C/C++.
• Practical knowledge of standard interconnects and I/O protocols used in modern chip designs, especially high-speed interfaces.
• Debugging skills using waveforms, logs, and protocol analyzers; ability to debug across the hardware/software boundary.
• Experience developing/debugging firmware and FPGA-based system solutions.
• Excellent communication and interpersonal skills; ability to work in international, cross-functional teams.
• Nice-to-have: specific experience with PCIe, CXL, or other leading-edge memory and I/O protocols.

Education Requirements

BS with a minimum of 10 years of relevant experience, or MS with a minimum of 7 years of relevant experience. The posting does not specify a required field of study or certifications.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.