Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud-Scale Machine Learning

Job Title

Sr. Physical Design Engineer - Static Timing Analysis (Annapurna Labs, AWS Cloud-Scale Machine Learning)

Role Summary

Work on physical design and static timing analysis (STA) for cloud-scale ML acceleration hardware, including platforms like AWS Inferentia. The role focuses on timing closure, constraint development, automation of STA flows, and cross-functional collaboration with RTL, architecture, and physical design teams.

Contribute technical leadership to improve performance, quality, and cost of large-scale hardware deployments.

Experience Level

Senior. Typical experience expectations: BS + 8 years, MS + 6 years, or PhD + 4 years in relevant fields; at least 3+ years performing Static Timing Analysis and 3+ years developing timing constraints.

Responsibilities

Core hands-on responsibilities and team interactions.

• Develop and maintain STA flows for block and full-chip analysis.
• Write, debug, and validate timing constraints for blocks and full-chip designs.
• Run static timing analysis, interpret results, and provide actionable feedback to design teams.
• Recommend and implement fixes (ECOs, constraint corrections) to resolve timing issues.
• Develop automation and scripts to run timing analysis and generate reports.
• Collaborate closely with physical design, RTL, and architecture teams throughout the design cycle.
• Mentor and guide junior engineers on STA best practices and flows.

Requirements

Must-have and preferred technical skills; degrees are listed separately under Education Requirements.

• Must-have: Strong knowledge of timing analysis fundamentals and STA tools (examples: Synopsys PrimeTime, Siemens/Ansys Tempus or equivalent); 3+ years hands-on STA experience; 3+ years timing-constraint development experience.
• Must-have: Experience scripting/automation using Perl, Python, or JavaScript; ability to develop robust scripts and reporting flows.
• Must-have: Understanding of ASIC physical design flow from RTL-to-GDSII and of sign-off activities such as IR/EM, physical verification, and DFT.
• Nice-to-have: Experience developing STA flows and ECO flows (examples: PT-DMSA, Tempus-ECO, Tweaker); mentoring or team leadership experience.
• Nice-to-have: Experience with advanced process nodes (16nm and below), parasitic extraction tools (STAR-RC, Quantus), circuit-level analysis (SPICE/SPECTRE), and timing of high-speed IO (DDR, HBM, PCIe, die-to-die interfaces).

Education Requirements

Degree and experience combinations specified: Bachelor of Science (BS) with ~8 years' experience, Master of Science (MS) with ~6 years' experience, or PhD with ~4 years' experience. Fields mentioned: Electrical Engineering or Computer Science.

About the Company

Company: KGS

KGS is a government and commercial contracting firm that provides engineering, technical, and staffing solutions, often supporting aerospace, defense, and IT projects for federal and industry customers.