Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

Job Title

Senior Physical Design (Static Timing Analysis) Engineer — Cloud-Scale Machine Learning (Annapurna Labs)

Role Summary

Lead static timing analysis (STA) efforts for block- and full-chip physical design of cloud server SoCs used in AWS data centers, including machine-learning acceleration hardware. Work within the Cloud-Scale Machine Learning Acceleration team to develop and maintain STA flows, constraints, and automation to improve timing closure, quality, and manufacturability at scale.

Experience Level

Senior. Posting specifies degree + experience combinations (see Education Requirements) and expects multiple years of hands-on STA and physical design experience; typical candidates have 6–8+ years of relevant ASIC/STA experience.

Responsibilities

Primary responsibilities include STA flow development, timing analysis, and collaboration across design teams.

• Develop and maintain block- and full-chip static timing analysis flows and automation scripts.
• Write, debug, and validate timing constraints for blocks and full-chip designs.
• Run STA runs using EDA tools and analyze results to identify timing issues.
• Provide actionable guidance to fix timing problems (generate ECOs, correct constraints).
• Generate timing reports and automate reporting for engineering teams.
• Collaborate closely with physical design, RTL, and architecture teams to achieve timing closure.

Requirements

Must-have technical skills and experience.

• Expertise in timing analysis fundamentals and STA methodologies.
• 3+ years performing Static Timing Analysis and 3+ years developing timing constraints.
• Experience with STA EDA tools (examples: Synopsys PrimeTime, Cadence Tempus, or similar).
• Proficiency in scripting (Perl, Python, or JavaScript) for automation and flow development.
• Understanding of ASIC physical design flow from RTL to GDSII and common sign-off activities (IR/EM, physical verification, DFT).

Education Requirements

Degree and experience requirements specified: Bachelor of Science (BS) in Electrical Engineering or Computer Science plus 8 years experience; Master of Science (MS) in EE/CS plus 6 years experience; or PhD in EE/CS plus 4 years experience. Fields called out: Electrical Engineering, Computer Science. (These degree+experience combinations were given in the posting.)

Preferred Qualifications

Nice-to-have skills that improve fit for the role.

• Experience mentoring, leading, or coaching engineers.
• Expertise developing STA flows and ECO flows (examples: PT-DMSA, Tempus-ECO, Tweaker).
• Experience with advanced process nodes (16nm or below) and parasitic extraction tools (STAR-RC, Cadence Quantus, or similar).
• Circuit-level analysis experience with SPICE/SPECTRE and timing of IO interfaces (DDR, HBM, PCIe, Die-to-Die).

About the Company

Company: Amazon Web Services

Headquarters: Seattle, Washington, USA

Amazon Web Services (AWS) provides a comprehensive and evolving cloud computing platform that includes infrastructure as a service (IaaS), platform as a service (PaaS), and software as a service (SaaS). AWS allows business and developers to use a wide range of cloud services for computing power, storage, and content delivery, among others, thus fostering innovation and enabling faster deployment of applications. AWS is designed to be scalable, flexible, and cost-effective across industries worldwide.