Sr. Physical Design Engineer - Static Timing Analysis

Job Title

Sr. Physical Design Engineer — Static Timing Analysis (Annapurna Labs, Cloud-Scale Machine Learning)

Role Summary

Senior physical design engineer on the Cloud-Scale Machine Learning Acceleration team responsible for static timing analysis (STA) for block and full-chip designs used in AWS data-center hardware (for example, Inferentia).

The role focuses on building and maintaining STA flows, writing and validating timing constraints, running sign-off analyses, guiding ECO fixes, and collaborating with physical design, RTL and architecture teams to improve performance, quality, and cost.

Experience Level

Senior-level. Candidates should be experienced in ASIC/SoC physical design with multiple years in timing analysis; the role requires hands-on STA experience (see Requirements for minimum STA experience).

Responsibilities

Accountabilities for this role include STA flow development, timing closure, and cross-team coordination.

• Develop and maintain block- and full-chip static timing analysis flows.
• Write, debug, and validate timing constraints for blocks and full-chip designs.
• Run STA, analyze results, and provide actionable feedback to designers and leads.
• Recommend and generate ECOs and guidance to fix timing issues.
• Automate timing runs and reporting via scripting and flow development.
• Collaborate with physical design, RTL, and architecture teams; participate in design reviews and closure planning.
• Provide technical leadership in applying new technologies to large-scale deployments.

Requirements

Must-have technical skills and practical experience required for immediate contribution.

• Must-have: Proficiency with scripting (Perl, Python, or JavaScript) for flow automation.
• Solid knowledge of timing analysis fundamentals and sign-off methodologies.
• Minimum 3+ years performing Static Timing Analysis and 3+ years developing timing constraints.
• Experience using STA tools such as Synopsys PrimeTime, Cadence Tempus, or equivalent.
• Understanding of ASIC physical design flow from RTL to GDSII.
• Familiarity with sign-off activities including IR/EM, physical verification, and DFT.

Nice-to-have:

• Experience mentoring or leading engineers and developing STA flows at block and full-chip scale.
• Expertise in ECO flows and tools (e.g., PT-DMSA, Tempus-ECO, Tweaker).
• Experience with advanced process nodes (16nm and below) and parasitic extraction tools (STAR-RC, Quantus).
• Circuit-level analysis experience (SPICE/SPECTRE) and timing of high-speed IOs (DDR, HBM, PCIe, die-to-die).

Education Requirements

Degree and experience expectations listed in the posting: BS + 8 years, MS + 6 years, or PhD + 4 years in Electrical Engineering (EE) or Computer Science (CS). No specific certifications were listed.

About the Company

Company: Amazon Web Services

Headquarters: Seattle, Washington, USA

Amazon Web Services (AWS) provides a comprehensive and evolving cloud computing platform that includes infrastructure as a service (IaaS), platform as a service (PaaS), and software as a service (SaaS). AWS allows business and developers to use a wide range of cloud services for computing power, storage, and content delivery, among others, thus fostering innovation and enabling faster deployment of applications. AWS is designed to be scalable, flexible, and cost-effective across industries worldwide.