Sr. Physical Design Engineer, Annapurna Labs

Job Title

Sr. Physical Design Engineer, Annapurna Labs

Role Summary

Join the Cloud-Scale Machine Learning Acceleration team at Annapurna Labs (AWS) to design and optimize custom SoCs used in AWS ML servers (inference and training). The role focuses on physical implementation, sign-off, and quality-of-result at datacenter scale.

The engineer will work across RTL, architecture, and EDA tool flows to drive physical closure, power/time/area trade-offs, IP integration, and production sign-off for advanced process nodes.

Experience Level

Senior. The position expects an experienced ASIC physical design engineer with industry experience (typical guidance: 6+ years in RTL-to-GDSII physical design; see Education Requirements for degree/experience combinations).

Responsibilities

Key responsibilities include delivering physical implementation and enabling robust sign-off for server-class SoCs.

• Collaborate with RTL and architecture teams to evaluate architectural feasibility and PPA trade-offs.
• Drive block and subsystem physical implementation: synthesis, floorplanning, pin/bus planning, place-and-route, power/clock distribution, congestion and timing closure, IR drop analysis, ECO and sign-off.
• Perform physical verification and ensure design meets sign-off criteria (timing, IR/EM, DRC/LVS/other checks).
• Develop and improve physical design methodologies and automation flows.
• Evaluate and integrate 3rd-party IP; specify IP requirements for physical integration.
• Collaborate with other physical design engineers and cross-functional teams to meet project schedules and quality targets.

Requirements

Must-have skills and domain experience required to perform the role.

• 6+ years of ASIC physical design experience (RTL-to-GDSII) with advanced nodes (examples: 7nm, 14/16nm, 20nm, 28nm).
• Hands-on experience with EDA tools for synthesis, floorplanning, place-and-route, timing closure, power distribution, congestion analysis, IR drop analysis, physical verification, and ECO.
• Proficiency scripting in Python, Perl, Bash, or PowerShell to create flows and automation.
• Deep understanding of sign-off activities including timing, IR/EM, and physical verification.
• Experience evaluating and integrating IP into physical design flows.

Nice-to-have:

• Experience mentoring or leading junior engineers.
• Expertise in developing CAD flows and formalizing physical implementation practices.
• Experience with device physics, custom/semi-custom implementation techniques, or system interfaces (DDR, PCIe, fabrics).
• Experience extracting design parameters, QOR metrics, and trend analysis.

Education Requirements

BS + 8 years or MS + 6 years in Electrical Engineering, Computer Science, or a related technical field (the posting specifies these degree-plus-experience combinations). Equivalent practical experience in ASIC physical design may be considered where stated.

About the Company

Company: KGS

KGS is a government and commercial contracting firm that provides engineering, technical, and staffing solutions, often supporting aerospace, defense, and IT projects for federal and industry customers.