Sr. Physical Design Engineer, Annapurna Labs

Job Title

Sr. Physical Design Engineer, Annapurna Labs

Role Summary

Join the Cloud-Scale Machine Learning Acceleration team to design and optimize custom SoCs for AWS ML servers (inference and training). The role focuses on physical implementation and sign-off of complex ASIC blocks and subsystems used in datacenter servers.

This position requires delivering high-quality physical designs, developing methodologies, and collaborating closely with RTL, architecture, and verification teams to meet power, performance, area, and manufacturability targets.

Experience Level

Senior. Requires multiple years of ASIC physical design experience; Basic Qualifications indicate 6+ years in ASIC physical design (see Education Requirements for degree guidance).

Responsibilities

Deliver physical implementation and closure for SoC blocks and subsystems and contribute to team methodologies.

• Drive IO/core subsystem and block implementation: synthesis, floorplanning, bus and pin planning, place & route.
• Design and validate power and clock distribution networks; perform congestion analysis and IR/EM analysis.
• Perform timing closure, timing sign-off activities, physical verification, ECOs, and final sign-off to GDSII.
• Collaborate with RTL, logic, and architecture teams to evaluate feasibility and trade-offs for power, performance, and area.
• Develop and improve physical design methodologies and flows.
• Evaluate third-party IP and specify/drive IP requirements in the physical domain.
• Work in a cross-functional team environment to integrate designs into server systems.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Must-have: 6+ years of ASIC physical design experience (RTL-to-GDSII) in advanced nodes (examples: 7nm, 14/16nm, 20nm, 28nm).
• Proven experience with block-level physical implementation steps: synthesis, floorplanning, bus/pin planning, place & route.
• Strong experience with power/clock distribution, congestion analysis, timing closure, IR drop/EM analysis, physical verification, and ECO sign-off.
• Familiarity with major EDA tool vendors and flows (examples: Cadence, Mentor Graphics, Synopsys).
• Experience scripting in Python, Perl, Bash, or PowerShell to automate flows.
• Nice-to-have: mentoring or leadership experience; developing CAD flows; 4+ years integrating IP and defining IP requirements; device physics and custom/semi-custom implementation techniques; experience across DDR, PCIe, fabrics; experience extracting QOR metrics and trend analysis.

Education Requirements

Basic Qualifications specify a Bachelor's degree plus 8 years' experience or a Master's degree plus 6 years' experience in Electrical Engineering or Computer Science (BS + 8 years or MS + 6 years in EE/CS). Equivalent practical experience is not explicitly stated.

About the Company

Company: KGS

KGS is a government and commercial contracting firm that provides engineering, technical, and staffing solutions, often supporting aerospace, defense, and IT projects for federal and industry customers.